Z8M( xL'ti,dra7-evmti,dra742ti,dra74ti,dra7& 7TI DRA742chosen=/ocp/serial@4806a000aliasesI/ocp/i2c@48070000N/ocp/i2c@48072000S/ocp/i2c@48060000X/ocp/i2c@4807a000]/ocp/i2c@4807c000b/ocp/serial@4806a000j/ocp/serial@4806c000r/ocp/serial@48020000z/ocp/serial@4806e000/ocp/serial@48066000/ocp/serial@48068000/ocp/serial@48420000/ocp/serial@48422000/ocp/serial@48424000/ocp/serial@4ae2b000&/ocp/ethernet@48484000/slave@48480200&/ocp/ethernet@48484000/slave@48480300/ocp/can@481cc000/ocp/can@481d0000/ocp/qspi@4b300000timerarm,armv7-timer0   &interrupt-controller@48211000arm,cortex-a15-gic@ H!H! H!@ H!`   &interrupt-controller@48281000&ti,omap5-wugen-mputi,omap4-wugen-mpu H(&cpuscpu@0cpuarm,cortex-a15 (<CcpuO]ocpu@1cpuarm,cortex-a15 (opp-tableoperating-points-v2-ti-cpuopp_nom@1000000000; , P0opp_od@1176000000FV @ @socti,omap-inframpu ti,omap5-mpumpuocpti,dra7-l3-nocsimple-busl3_main_1l3_main_2  DE  l4@4a000000ti,dra7-l4-cfgsimple-bus J"scm@2000ti,dra7-scm-coresimple-bus   scm_conf@0sysconsimple-bus  pbias_regulator@e00ti,pbias-dra7ti,pbias-omap pbias_mmc_omap5pbias_mmc_omap5w@,-clocksdss_deshdcp_clk@558Dti,gate-clock< Q Xehrpwm0_tbclk@558Dti,gate-clock< Q Xehrpwm1_tbclk@558Dti,gate-clock< Q Xehrpwm2_tbclk@558Dti,gate-clock< Q Xsys_32k_ckD ti,mux-clock< Q LLpinmux@1400ti,dra7-padconfpinctrl-single h^m ?dcan1_pins_defaultdcan1_pins_sleepmmc1_pins_default8lTX\`dhmmc2_pins_defaultPscm_conf@1c04syscon  scm_conf@1c24syscon $$dma-router@b78ti,dra7-dma-crossbar x dma-router@c78ti,dra7-dma-crossbar x|cm_core_aon@5000ti,dra7-cm-core-aon P clocksatl_clkin0_ckDti,dra7-atl-clock<??atl_clkin1_ckDti,dra7-atl-clock<>>atl_clkin2_ckDti,dra7-atl-clock<==atl_clkin3_ckDti,dra7-atl-clock<<<hdmi_clkin_ckD fixed-clock--mlb_clkin_ckD fixed-clockmlbp_clkin_ckD fixed-clockpciesref_acs_clk_ckD fixed-clockVVref_clkin0_ckD fixed-clockAAref_clkin1_ckD fixed-clockBBref_clkin2_ckD fixed-clockCCref_clkin3_ckD fixed-clockDDrmii_clk_ckD fixed-clockmmsdvenc_clkin_ckD fixed-clocksecure_32k_clk_src_ckD fixed-clocksys_clk32_crystal_ckD fixed-clock  sys_clk32_pseudo_ckDfixed-factor-clock< b  virt_12000000_ckD fixed-clockzzvirt_13000000_ckD fixed-clock]@virt_16800000_ckD fixed-clockY||virt_19200000_ckD fixed-clock$}}virt_20000000_ckD fixed-clock1-{{virt_26000000_ckD fixed-clock~~virt_27000000_ckD fixed-clockvirt_38400000_ckD fixed-clockIsys_clkin2D fixed-clockX@@usb_otg_clkin_ckD fixed-clockvideo1_clkin_ckD fixed-clock66video1_m2_clkin_ckD fixed-clock,,video2_clkin_ckD fixed-clock77video2_m2_clkin_ckD fixed-clock++dpll_abe_ck@1e0Dti,omap4-dpll-m4xen-clock< dpll_abe_x2_ckDti,omap4-dpll-x2-clock<dpll_abe_m2x2_ck@1f0Dti,divider-clock<  2Iabe_clk@108Dti,divider-clock< `dpll_abe_m2_ck@1f0Dti,divider-clock<  2Ikkdpll_abe_m3x2_ck@1f4Dti,divider-clock<  2Idpll_core_byp_mux@12cD ti,mux-clock<Q ,dpll_core_ck@120Dti,omap4-dpll-core-clock<  $,(dpll_core_x2_ckDti,omap4-dpll-x2-clock<dpll_core_h12x2_ck@13cDti,divider-clock<?  <2Impu_dpll_hs_clk_divDfixed-factor-clock< dpll_mpu_ck@160Dti,omap5-mpu-dpll-clock< `dlhdpll_mpu_m2_ck@170Dti,divider-clock<  p2Impu_dclk_divDfixed-factor-clock< dsp_dpll_hs_clk_divDfixed-factor-clock< dpll_dsp_byp_mux@240D ti,mux-clock<Q @dpll_dsp_ck@234Dti,omap4-dpll-clock< 48@<dpll_dsp_m2_ck@244Dti,divider-clock<  D2Iiva_dpll_hs_clk_divDfixed-factor-clock<   dpll_iva_byp_mux@1acD ti,mux-clock< Q !!dpll_iva_ck@1a0Dti,omap4-dpll-clock<! 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mmc1_clk32k@1328Dti,gate-clock<LQ (mmc2_clk32k@1330Dti,gate-clock<LQ 0mmc3_clk32k@1820Dti,gate-clock<LQ  mmc4_clk32k@1828Dti,gate-clock<LQ (sata_ref_clk@1388Dti,gate-clock<Q usb_otg_ss1_refclk960m@13f0Dti,gate-clock<jQ usb_otg_ss2_refclk960m@1340Dti,gate-clock<jQ @usb_phy1_always_on_clk32k@640Dti,gate-clock<LQ @usb_phy2_always_on_clk32k@688Dti,gate-clock<LQ usb_phy3_always_on_clk32k@698Dti,gate-clock<LQ atl_dpll_clk_mux@c00D ti,mux-clock<L67-Q llatl_gfclk_mux@c00D ti,mux-clock < klQ rmii_50mhz_clk_mux@13d0D ti,mux-clock<5mQ gmac_rft_clk_mux@13d0D ti,mux-clock<67k- Q gpu_core_gclk_mux@1220D ti,mux-clock <nopQ  gpu_hyd_gclk_mux@1220D ti,mux-clock <nopQ  l3instr_ts_gclk_div@e50Dti,divider-clock<qQ P v mcasp2_ahclkr_mux@1860D ti,mux-clock8<9:;<=>?@ABCDEFQ `mcasp2_ahclkx_mux@1860D ti,mux-clock8<9:;<=>?@ABCDEFQ `mcasp2_aux_gfclk_mux@1860D ti,mux-clock<GHIJQ `mcasp3_ahclkx_mux@1868D ti,mux-clock8<9:;<=>?@ABCDEFQ hmcasp3_aux_gfclk_mux@1868D ti,mux-clock<GHIJQ hmcasp4_ahclkx_mux@1898D ti,mux-clock8<9:;<=>?@ABCDEFQ mcasp4_aux_gfclk_mux@1898D ti,mux-clock<GHIJQ mcasp5_ahclkx_mux@1878D ti,mux-clock8<9:;<=>?@ABCDEFQ xmcasp5_aux_gfclk_mux@1878D ti,mux-clock<GHIJQ xmcasp6_ahclkx_mux@1904D ti,mux-clock8<9:;<=>?@ABCDEFQ mcasp6_aux_gfclk_mux@1904D ti,mux-clock<GHIJQ mcasp7_ahclkx_mux@1908D ti,mux-clock8<9:;<=>?@ABCDEFQ mcasp7_aux_gfclk_mux@1908D ti,mux-clock<GHIJQ mcasp8_ahclkx_mux@1890D ti,mux-clock8<9:;<=>?@ABCDEFQ mcasp8_aux_gfclk_mux@1890D ti,mux-clock<GHIJQ mmc1_fclk_mux@1328D ti,mux-clock<rSQ (ssmmc1_fclk_div@1328Dti,divider-clock<sQ (`mmc2_fclk_mux@1330D ti,mux-clock<rSQ 0ttmmc2_fclk_div@1330Dti,divider-clock<tQ 0`mmc3_gfclk_mux@1820D ti,mux-clock<RSQ  uummc3_gfclk_div@1820Dti,divider-clock<uQ  `mmc4_gfclk_mux@1828D ti,mux-clock<RSQ (vvmmc4_gfclk_div@1828Dti,divider-clock<vQ (`qspi_gfclk_mux@1838D ti,mux-clock<rwQ 8xxqspi_gfclk_div@1838Dti,divider-clock<xQ 8`timer10_gfclk_mux@1728D ti,mux-clock,<KL@ABCDMNOPQ (timer11_gfclk_mux@1730D ti,mux-clock,<KL@ABCDMNOPQ 0timer13_gfclk_mux@17c8D ti,mux-clock,<KL@ABCDMNOPQ timer14_gfclk_mux@17d0D ti,mux-clock,<KL@ABCDMNOPQ timer15_gfclk_mux@17d8D ti,mux-clock,<KL@ABCDMNOPQ timer16_gfclk_mux@1830D ti,mux-clock,<KL@ABCDMNOPQ 0timer2_gfclk_mux@1738D ti,mux-clock,<KL@ABCDMNOPQ 8timer3_gfclk_mux@1740D ti,mux-clock,<KL@ABCDMNOPQ @timer4_gfclk_mux@1748D ti,mux-clock,<KL@ABCDMNOPQ Htimer9_gfclk_mux@1750D ti,mux-clock,<KL@ABCDMNOPQ Puart1_gfclk_mux@1840D ti,mux-clock<RSQ @uart2_gfclk_mux@1848D ti,mux-clock<RSQ Huart3_gfclk_mux@1850D ti,mux-clock<RSQ Puart4_gfclk_mux@1858D ti,mux-clock<RSQ Xuart5_gfclk_mux@1870D ti,mux-clock<RSQ puart7_gfclk_mux@18d0D ti,mux-clock<RSQ uart8_gfclk_mux@18e0D ti,mux-clock<RSQ uart9_gfclk_mux@18e8D ti,mux-clock<RSQ vip1_gclk_mux@1020D ti,mux-clock< yQ  vip2_gclk_mux@1028D ti,mux-clock< yQ (vip3_gclk_mux@1030D ti,mux-clock< yQ 0clockdomainscoreaon_clkdmti,clockdomain<`l4@4ae00000ti,dra7-l4-wkupsimple-bus Jcounter@4000ti,omap-counter32k @@ counter_32kprm@6000 ti,dra7-prm `0 clockssys_clkin1@110D ti,mux-clock<z{|}~ 2abe_dpll_sys_clk_mux@118D ti,mux-clock<@ abe_dpll_bypass_clk_mux@114D ti,mux-clock<L abe_dpll_clk_mux@10cD ti,mux-clock<L  abe_24m_fclk@11cDti,divider-clock< v99aess_fclk@178Dti,divider-clock< xabe_giclk_div@174Dti,divider-clock< tMMabe_lp_clk_div@1d8Dti,divider-clock< v abe_sys_clk_div@120Dti,divider-clock<  ::adc_gfclk_mux@1dcD ti,mux-clock <@L sys_clk1_dclk_div@1c8Dti,divider-clock<@ `sys_clk2_dclk_div@1ccDti,divider-clock<@@ `per_abe_x1_dclk_div@1bcDti,divider-clock<k@ `dsp_gclk_div@18cDti,divider-clock<@ `gpu_dclk@1a0Dti,divider-clock<p@ `emif_phy_dclk_div@190Dti,divider-clock<@ `gmac_250m_dclk_div@19cDti,divider-clock<@ `gmac_main_clkDfixed-factor-clock< l3init_480m_dclk_div@1acDti,divider-clock<c@ `usb_otg_dclk_div@184Dti,divider-clock<@ `sata_dclk_div@1c0Dti,divider-clock<@ `pcie2_dclk_div@1b8Dti,divider-clock<@ `pcie_dclk_div@1b4Dti,divider-clock<@ `emu_dclk_div@194Dti,divider-clock<@ `secure_32k_dclk_div@1c4Dti,divider-clock<@ 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