)8'0(h&)Qualcomm Technologies, Inc. MSM 8996 MTP&2qcom,msm8996-mtpchosen=serial0memoryImemoryUcpus&cpu@0Icpu 2qcom,kryoUYpscigx~l2-cache2cachex~cpu@1Icpu 2qcom,kryoUYpscigx~cpu@100Icpu 2qcom,kryoUYpscigx~l2-cache2cachex~cpu@101Icpu 2qcom,kryoUYpscigx~cpu-mapcluster0core0core1cluster1core0core1timer2arm,armv8-timer0   clocksxo_board 2fixed-clock$ xo_boardsleep_clk 2fixed-clock sleep_clkpsci 2arm,psci-1.0`smcsoc& 2simple-businterrupt-controller@9bc0000 2arm,gic-v3U    x~clock-controller@3000002qcom,gcc-msm8996*7U0 x~spi@075750002qcom,spi-qup-v2.2.1UWP _Kom Rcoreiface^defaultsleepl v & disabledi2c@075b50002qcom,i2c-qup-v2.2.1U[P eK Rifacecore^defaultsleepl v & disabledserial@75b0000%2qcom,msm-uartdm-v1.4qcom,msm-uartdmU[ rK Rcoreifaceokayi2c@075b60002qcom,i2c-qup-v2.2.1U[` fK Rifacecore^defaultsleepl v& disabledserial@75b1000%2qcom,msm-uartdm-v1.4qcom,msm-uartdmU[ sK Rcoreiface disabledi2c@075770002qcom,i2c-qup-v2.2.1UWp aKmv Rifacecore^defaultsleeplv& disabledspi@075ba0002qcom,spi-qup-v2.2.1U[ kK Rcoreiface^defaultsleeplv& disabledsdhci@74a4900 disabled2qcom,sdhci-msm-v4UJIJ@hc_memcore_mem}hc_irqpwr_irq RifacecoreKhgpinctrl@10100002qcom,msm8996-pinctrlU0 blsp1_spi0_defaultx ~ pinmux blsp_spi1gpio0gpio1gpio3pinmux_csgpiogpio2pinconfgpio0gpio1gpio3 pinconf_csgpio2blsp1_spi0_sleepx ~ pinmuxgpiogpio0gpio1gpio2gpio3pinconfgpio0gpio1gpio2gpio3blsp1_i2c2_defaultx~pinmux blsp_i2c3gpio47gpio48pinconfgpio47gpio48blsp1_i2c2_sleepx~pinmuxgpiogpio47gpio48pinconfgpio47gpio48blsp2_i2c0x ~ pinmux blsp_i2c7gpio55gpio56pinconfgpio55gpio56blsp2_i2c0_sleepx ~ pinmuxgpiogpio55gpio56pinconfgpio55gpio56blsp2_uart1_2pinspinmux blsp_uart8 gpio4gpio5pinconf gpio4gpio5blsp2_uart1_2pins_sleeppinmuxgpio gpio4gpio5pinconf gpio4gpio5blsp2_uart1_4pinspinmux blsp_uart8gpio4gpio5gpio6gpio7pinconfgpio4gpio5gpio6gpio7blsp2_uart1_4pins_sleeppinmuxgpiogpio4gpio5gpio6gpio7pinconfgpio4gpiio5gpio6gpio7blsp2_i2c1x ~ pinmux blsp_i2c8 gpio6gpio7pinconf gpio6gpio7blsp2_i2c1_sleepx~pinmuxgpio gpio6gpio7pinconf gpio6gpio7blsp2_uart2_2pinspinmux blsp_uart9gpio49gpio50pinconfgpio49gpio50blsp2_uart2_2pins_sleeppinmuxgpiogpio49gpio50pinconfgpio49gpio50blsp2_uart2_4pinspinmux blsp_uart9gpio49gpio50gpio51gpio52pinconfgpio49gpio50gpio51gpio52blsp2_uart2_4pins_sleeppinmuxgpiogpio49gpio50gpio51gpio52pinconfgpio49gpio50gpio51gpio52blsp2_spi5_defaultx~pinmux blsp_spi12gpio85gpio86gpio88pinmux_csgpiogpio87pinconfgpio85gpio86gpio88 pinconf_csgpio87blsp2_spi5_sleepx~pinmuxgpiogpio85gpio86gpio87gpio88pinconfgpio85gpio86gpio87gpio88sdc2_clk_onconfig sdc2_clksdc2_clk_offconfig sdc2_clksdc2_cmd_onconfig sdc2_cmd  sdc2_cmd_offconfig sdc2_cmd sdc2_data_onconfig sdc2_data  sdc2_data_offconfig sdc2_data timer@09840000&2arm,armv7-timer-memU $frame@9850000U  frame@9870000 U  disabledframe@9880000 !U  disabledframe@9890000 "U  disabledframe@98a0000 #U  disabledframe@98b0000 $U  disabledframe@98c0000 %U  disabledqcom,spmi@400f0002qcom,spmi-pmic-arb(U@ !corechnlsobsrvrintrcnfg periph_irq F&.&clock-controller@8c00002qcom,mmcc-msm8996*7U(;  K%1|0G:i98p1,@x~aliases`/soc/serial@75b0000 modelinterrupt-parent#address-cells#size-cellscompatiblestdout-pathdevice_typeregenable-methodnext-level-cachelinux,phandlecache-levelcpuinterrupts#clock-cellsclock-frequencyclock-output-namesranges#interrupt-cellsinterrupt-controller#redistributor-regionsredistributor-stride#reset-cells#power-domain-cellsclocksclock-namespinctrl-namespinctrl-0pinctrl-1statusreg-namesinterrupt-namesbus-widthgpio-controller#gpio-cellsfunctionpinsdrive-strengthbias-disableoutput-highbias-pull-downbias-pull-upframe-numberqcom,eeqcom,channelassigned-clocksassigned-clock-ratesserial0