/v8%( r$;compulab,cl-som-am57xti,am5728ti,dra742ti,dra74ti,dra7&7CompuLab CL-SOM-AM57xchosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/i2c@4807a000Q/ocp/i2c@4807c000V/ocp/serial@4806a000^/ocp/serial@4806c000f/ocp/serial@48020000n/ocp/serial@4806e000v/ocp/serial@48066000~/ocp/serial@48068000/ocp/serial@48420000/ocp/serial@48422000/ocp/serial@48424000/ocp/serial@4ae2b000&/ocp/ethernet@48484000/slave@48480200&/ocp/ethernet@48484000/slave@48480300/ocp/can@481cc000/ocp/can@481d0000/ocp/qspi@4b300000memorymemoryـ timerarm,armv7-timer0   &interrupt-controller@48211000arm,cortex-a15-gic H!H! H!@ H!`   &interrupt-controller@48281000&ti,omap5-wugen-mputi,omap4-wugen-mpuH(&socti,omap-inframpu ti,omap5-mpumpuocpti,dra7-l3-nocsimple-bus&l3_main_1l3_main_2DE - l4@4a000000ti,dra7-l4-cfgsimple-bus &J"scm@2000ti,dra7-scm-coresimple-bus  & scm_conf@0sysconsimple-bus &pbias_regulatorti,pbias-dra7ti,pbias-omapApbias_mmc_omap5Hpbias_mmc_omap5Ww@o-clocksdss_deshdcp_clkti,gate-clockXpinmux@1400ti,dra7-padconfpinctrl-singleh ?leds_pins_default|i2c1_pins_defaulti2c3_pins_default  i2c4_pins_default  tps659038_pins_defaultmmc2_pins_defaultPpinmux_qspi1_pins0tcpsw_pins_defaultPTX\`dhlptx|cpsw_pins_sleepPTX\`dhlptx|davinci_mdio_pins_defaultdavinci_mdio_pins_sleeppinmux_ads7846_pinsdmcasp3_pins_default $(,0mcasp3_pins_sleep $(,0scm_conf@1c04syscon cm_core_aon@5000ti,dra7-cm-core-aonP clocksatl_clkin0_ckti,dra7-atl-clock77atl_clkin1_ckti,dra7-atl-clock66atl_clkin2_ckti,dra7-atl-clock55atl_clkin3_ckti,dra7-atl-clock44hdmi_clkin_ck fixed-clock%%mlb_clkin_ck fixed-clockmlbp_clkin_ck fixed-clockpciesref_acs_clk_ck fixed-clockNNref_clkin0_ck fixed-clock99ref_clkin1_ck fixed-clock::ref_clkin2_ck fixed-clock;;ref_clkin3_ck fixed-clock<<rmii_clk_ck fixed-clocksdvenc_clkin_ck fixed-clocksecure_32k_clk_src_ck fixed-clocksys_32k_ck fixed-clockDDvirt_12000000_ck fixed-clockrrvirt_13000000_ck fixed-clock]@virt_16800000_ck fixed-clockYttvirt_19200000_ck fixed-clock$uuvirt_20000000_ck fixed-clock1-ssvirt_26000000_ck fixed-clockvvvirt_27000000_ck fixed-clockwwvirt_38400000_ck fixed-clockIxxsys_clkin2 fixed-clockX88usb_otg_clkin_ck fixed-clock~~video1_clkin_ck fixed-clock..video1_m2_clkin_ck fixed-clock$$video2_clkin_ck fixed-clock//video2_m2_clkin_ck fixed-clock##dpll_abe_ckti,omap4-dpll-m4xen-clock  dpll_abe_x2_ckti,omap4-dpll-x2-clock   dpll_abe_m2x2_ckti,divider-clock $;  abe_clkti,divider-clock Rzzdpll_abe_m2_ckti,divider-clock $;ccdpll_abe_m3x2_ckti,divider-clock $;  dpll_core_byp_mux ti,mux-clock ,dpll_core_ckti,omap4-dpll-core-clock  $,(dpll_core_x2_ckti,omap4-dpll-x2-clockdpll_core_h12x2_ckti,divider-clock?<$;mpu_dpll_hs_clk_divfixed-factor-clockhsdpll_mpu_ckti,omap5-mpu-dpll-clock `dlhdpll_mpu_m2_ckti,divider-clockp$;mpu_dclk_divfixed-factor-clockhsdsp_dpll_hs_clk_divfixed-factor-clockhsdpll_dsp_byp_mux ti,mux-clock @dpll_dsp_ckti,omap4-dpll-clock 48@<dpll_dsp_m2_ckti,divider-clockD$;||iva_dpll_hs_clk_divfixed-factor-clockhsdpll_iva_byp_mux ti,mux-clock dpll_iva_ckti,omap4-dpll-clock dpll_iva_m2_ckti,divider-clock$;iva_dclkfixed-factor-clockhsdpll_gpu_byp_mux ti,mux-clock dpll_gpu_ckti,omap4-dpll-clock dpll_gpu_m2_ckti,divider-clock$;hhdpll_core_m2_ckti,divider-clock0$;core_dpll_out_dclk_divfixed-factor-clockhsdpll_ddr_byp_mux ti,mux-clock dpll_ddr_ckti,omap4-dpll-clock   dpll_ddr_m2_ckti,divider-clock  $;}}dpll_gmac_byp_mux ti,mux-clock !!dpll_gmac_ckti,omap4-dpll-clock !""dpll_gmac_m2_ckti,divider-clock"$;eevideo2_dclk_divfixed-factor-clock#hsvideo1_dclk_divfixed-factor-clock$hshdmi_dclk_divfixed-factor-clock%hsper_dpll_hs_clk_divfixed-factor-clock hsRRusb_dpll_hs_clk_divfixed-factor-clock hsVVeve_dpll_hs_clk_divfixed-factor-clockhs&&dpll_eve_byp_mux ti,mux-clock &''dpll_eve_ckti,omap4-dpll-clock '((dpll_eve_m2_ckti,divider-clock($;))eve_dclk_divfixed-factor-clock)hsdpll_core_h13x2_ckti,divider-clock?@$;dpll_core_h14x2_ckti,divider-clock?D$;ffdpll_core_h22x2_ckti,divider-clock?T$;00dpll_core_h23x2_ckti,divider-clock?X$;qqdpll_core_h24x2_ckti,divider-clock?\$;dpll_ddr_x2_ckti,omap4-dpll-x2-clock **dpll_ddr_h11x2_ckti,divider-clock*?($;dpll_dsp_x2_ckti,omap4-dpll-x2-clock++dpll_dsp_m3x2_ckti,divider-clock+H$;dpll_gmac_x2_ckti,omap4-dpll-x2-clock",,dpll_gmac_h11x2_ckti,divider-clock,?$;--dpll_gmac_h12x2_ckti,divider-clock,?$;dpll_gmac_h13x2_ckti,divider-clock,?$;dpll_gmac_m3x2_ckti,divider-clock,$;gmii_m_clk_divfixed-factor-clock-hshdmi_clk2_divfixed-factor-clock%hsBBhdmi_div_clkfixed-factor-clock%hsHHl3_iclk_divti,divider-clockRl4_root_clk_divfixed-factor-clockhsvideo1_clk2_divfixed-factor-clock.hs@@video1_div_clkfixed-factor-clock.hsFFvideo2_clk2_divfixed-factor-clock/hsAAvideo2_div_clkfixed-factor-clock/hsGGipu1_gfclk_mux ti,mux-clock 0 mcasp1_ahclkr_mux ti,mux-clock8123456789:;<=>Pmcasp1_ahclkx_mux ti,mux-clock8123456789:;<=>Pmcasp1_aux_gfclk_mux ti,mux-clock?@ABPtimer5_gfclk_mux ti,mux-clock0CD89:;<EFGHIXtimer6_gfclk_mux ti,mux-clock0CD89:;<EFGHI`timer7_gfclk_mux ti,mux-clock0CD89:;<EFGHIhtimer8_gfclk_mux ti,mux-clock0CD89:;<EFGHIpuart6_gfclk_mux ti,mux-clockJKdummy_ck fixed-clockclockdomainscm_core@8000ti,dra7-cm-core0clocksdpll_pcie_ref_ckti,omap4-dpll-clock  LLdpll_pcie_ref_m2ldo_ckti,divider-clockL$;MMapll_pcie_in_clk_mux@4ae06118 ti,mux-clockMNOOapll_pcie_ckti,dra7-apll-clockOL PPoptfclk_pciephy1_32khz@4a0093b0ti,gate-clockDoptfclk_pciephy2_32khz@4a0093b8ti,gate-clockDoptfclk_pciephy_div@4a00821cti,divider-clockP}QQoptfclk_pciephy1_clk@4a0093b0ti,gate-clockP optfclk_pciephy2_clk@4a0093b8ti,gate-clockP optfclk_pciephy1_div_clk@4a0093b0ti,gate-clockQ optfclk_pciephy2_div_clk@4a0093b8ti,gate-clockQ apll_pcie_clkvcoldofixed-factor-clockPhsapll_pcie_clkvcoldo_divfixed-factor-clockPhsapll_pcie_m2_ckfixed-factor-clockPhsdpll_per_byp_mux ti,mux-clock RLSSdpll_per_ckti,omap4-dpll-clock S@DLHTTdpll_per_m2_ckti,divider-clockTP$;UUfunc_96m_aon_dclk_divfixed-factor-clockUhsdpll_usb_byp_mux ti,mux-clock VWWdpll_usb_ckti,omap4-dpll-j-type-clock WXXdpll_usb_m2_ckti,divider-clockX$;[[dpll_pcie_ref_m2_ckti,divider-clockL$;dpll_per_x2_ckti,omap4-dpll-x2-clockTYYdpll_per_h11x2_ckti,divider-clockY?X$;ZZdpll_per_h12x2_ckti,divider-clockY?\$;^^dpll_per_h13x2_ckti,divider-clockY?`$;oodpll_per_h14x2_ckti,divider-clockY?d$;ggdpll_per_m2x2_ckti,divider-clockYP$;KKdpll_usb_clkdcoldofixed-factor-clockXhs]]func_128m_clkfixed-factor-clockZhsjjfunc_12m_fclkfixed-factor-clockKhsfunc_24m_clkfixed-factor-clockUhs33func_48m_fclkfixed-factor-clockKhsJJfunc_96m_fclkfixed-factor-clockKhsl3init_60m_fclkti,divider-clock[}clkout2_clkti,gate-clock\l3init_960m_gfclkti,gate-clock]bbdss_32khz_clkti,gate-clockD  dss_48mhz_clkti,gate-clockJ  dss_dss_clkti,gate-clock^ dss_hdmi_clkti,gate-clock_  dss_video1_clkti,gate-clock`  dss_video2_clkti,gate-clocka  gpio2_dbclkti,gate-clockD`gpio3_dbclkti,gate-clockDhgpio4_dbclkti,gate-clockDpgpio5_dbclkti,gate-clockDxgpio6_dbclkti,gate-clockDgpio7_dbclkti,gate-clockDgpio8_dbclkti,gate-clockDmmc1_clk32kti,gate-clockD(mmc2_clk32kti,gate-clockD0mmc3_clk32kti,gate-clockD mmc4_clk32kti,gate-clockD(sata_ref_clkti,gate-clock usb_otg_ss1_refclk960mti,gate-clockbusb_otg_ss2_refclk960mti,gate-clockb@usb_phy1_always_on_clk32kti,gate-clockD@usb_phy2_always_on_clk32kti,gate-clockDusb_phy3_always_on_clk32kti,gate-clockDatl_dpll_clk_mux ti,mux-clockD./% ddatl_gfclk_mux ti,mux-clock cd gmac_gmii_ref_clk_divti,divider-clocke}gmac_rft_clk_mux ti,mux-clock./c%gpu_core_gclk_mux ti,mux-clock fgh gpu_hyd_gclk_mux ti,mux-clock fgh l3instr_ts_gclk_divti,divider-clockiP } mcasp2_ahclkr_mux ti,mux-clock8123456789:;<=>`mcasp2_ahclkx_mux ti,mux-clock8123456789:;<=>`mcasp2_aux_gfclk_mux ti,mux-clock?@AB`mcasp3_ahclkx_mux ti,mux-clock8123456789:;<=>hmcasp3_aux_gfclk_mux ti,mux-clock?@ABhmcasp4_ahclkx_mux ti,mux-clock8123456789:;<=>mcasp4_aux_gfclk_mux ti,mux-clock?@ABmcasp5_ahclkx_mux ti,mux-clock8123456789:;<=>xmcasp5_aux_gfclk_mux ti,mux-clock?@ABxmcasp6_ahclkx_mux ti,mux-clock8123456789:;<=>mcasp6_aux_gfclk_mux ti,mux-clock?@ABmcasp7_ahclkx_mux ti,mux-clock8123456789:;<=>mcasp7_aux_gfclk_mux ti,mux-clock?@ABmcasp8_ahclk_mux ti,mux-clock8123456789:;<=>mcasp8_aux_gfclk_mux ti,mux-clock?@ABmmc1_fclk_mux ti,mux-clockjK(kkmmc1_fclk_divti,divider-clockk(Rmmc2_fclk_mux ti,mux-clockjK0llmmc2_fclk_divti,divider-clockl0Rmmc3_gfclk_mux ti,mux-clockJK mmmmc3_gfclk_divti,divider-clockm Rmmc4_gfclk_mux ti,mux-clockJK(nnmmc4_gfclk_divti,divider-clockn(Rqspi_gfclk_mux ti,mux-clockjo8ppqspi_gfclk_divti,divider-clockp8Rtimer10_gfclk_mux ti,mux-clock,CD89:;<EFGH(timer11_gfclk_mux ti,mux-clock,CD89:;<EFGH0timer13_gfclk_mux ti,mux-clock,CD89:;<EFGHtimer14_gfclk_mux ti,mux-clock,CD89:;<EFGHtimer15_gfclk_mux ti,mux-clock,CD89:;<EFGHtimer16_gfclk_mux ti,mux-clock,CD89:;<EFGH0timer2_gfclk_mux ti,mux-clock,CD89:;<EFGH8timer3_gfclk_mux ti,mux-clock,CD89:;<EFGH@timer4_gfclk_mux ti,mux-clock,CD89:;<EFGHHtimer9_gfclk_mux ti,mux-clock,CD89:;<EFGHPuart1_gfclk_mux ti,mux-clockJK@uart2_gfclk_mux ti,mux-clockJKHuart3_gfclk_mux ti,mux-clockJKPuart4_gfclk_mux ti,mux-clockJKXuart5_gfclk_mux ti,mux-clockJKpuart7_gfclk_mux ti,mux-clockJKuart8_gfclk_mux ti,mux-clockJKuart9_gfclk_mux ti,mux-clockJKvip1_gclk_mux ti,mux-clockq vip2_gclk_mux ti,mux-clockq(vip3_gclk_mux ti,mux-clockq0clockdomainscoreaon_clkdmti,clockdomainXl4@4ae00000ti,dra7-l4-wkupsimple-bus &Jcounter@4000ti,omap-counter32k@@ counter_32kprm@6000 ti,dra7-prm`0 clockssys_clkin1 ti,mux-clockrstuvwx$  abe_dpll_sys_clk_mux ti,mux-clock 8yyabe_dpll_bypass_clk_mux ti,mux-clockyDabe_dpll_clk_mux ti,mux-clockyD abe_24m_fclkti,divider-clock }11aess_fclkti,divider-clockzx{{abe_giclk_divti,divider-clock{tEEabe_lp_clk_divti,divider-clock } abe_sys_clk_divti,divider-clock  22adc_gfclk_mux ti,mux-clock  8Dsys_clk1_dclk_divti,divider-clock @Rsys_clk2_dclk_divti,divider-clock8@Rper_abe_x1_dclk_divti,divider-clockc@Rdsp_gclk_divti,divider-clock|@Rgpu_dclkti,divider-clockh@Remif_phy_dclk_divti,divider-clock}@Rgmac_250m_dclk_divti,divider-clocke@Rl3init_480m_dclk_divti,divider-clock[@Rusb_otg_dclk_divti,divider-clock~@Rsata_dclk_divti,divider-clock @Rpcie2_dclk_divti,divider-clock@Rpcie_dclk_divti,divider-clock@Remu_dclk_divti,divider-clock @Rsecure_32k_dclk_divti,divider-clock@Rclkoutmux0_clk_mux ti,mux-clockXXIIclkoutmux1_clk_mux ti,mux-clockX\clkoutmux2_clk_mux ti,mux-clockX`\\custefuse_sys_gfclk_divfixed-factor-clock hseve_clk ti,mux-clock)hdmi_dpll_clk_mux ti,mux-clock 8d__mlb_clkti,divider-clock@4R==mlbp_clkti,divider-clock@0R>>per_abe_x1_gfclk2_divti,divider-clockc@8R??timer_sys_clk_divti,divider-clock DCCvideo1_dpll_clk_mux ti,mux-clock 8h``video2_dpll_clk_mux ti,mux-clock 8laawkupaon_iclk_mux ti,mux-clock iigpio1_dbclkti,gate-clockD8dcan1_sys_clk_mux ti,mux-clock 8timer1_gfclk_mux ti,mux-clock,CD89:;<EFGH@uart10_gfclk_mux ti,mux-clockJKclockdomainsaxi@0 simple-bus&QQ0 pcie@51000000 ti,dra7-pcieQ Q L rc_dbicsti_confconfigpci0&0 00pcie1 pcie-phy0`interrupt-controlleraxi@1 simple-bus&QQ00 disabledpcie@51000000 ti,dra7-pcieQ Q L rc_dbicsti_confconfigcdpci0&0000pcie2 pcie-phy0`interrupt-controllerbandgap@4a0021e00J! J#, J#,J#Ngpio@48055000ti,omap4-gpioHP gpio2>NokayZgpio@48057000ti,omap4-gpioHp gpio3>NokayZgpio@48059000ti,omap4-gpioH gpio4>Ngpio@4805b000ti,omap4-gpioH gpio5>Ngpio@4805d000ti,omap4-gpioH gpio6>Ngpio@48051000ti,omap4-gpioH gpio7>Ngpio@48053000ti,omap4-gpioH0 tgpio8>Nserial@4806a000ti,dra742-uartti,omap4-uartH-Cuart1l disabledn12stxrxserial@4806c000ti,dra742-uartti,omap4-uartH Duart2l disabledn34stxrxserial@48020000ti,dra742-uartti,omap4-uartH Euart3l disabledn56stxrxserial@4806e000ti,dra742-uartti,omap4-uartH Auart4l disabledn78stxrxserial@48066000ti,dra742-uartti,omap4-uartH` duart5l disabledn?@stxrxserial@48068000ti,dra742-uartti,omap4-uartH euart6l disablednOPstxrxserial@48420000ti,dra742-uartti,omap4-uartHB uart7l disabledserial@48422000ti,dra742-uartti,omap4-uartHB  uart8l disabledserial@48424000ti,dra742-uartti,omap4-uartHB@ uart9l disabledserial@4ae2b000ti,dra742-uartti,omap4-uartJ uart10l disabledmailbox@4a0f4000ti,omap4-mailboxJ@$ mailbox1} disabledmailbox@4883a000ti,omap4-mailboxH0 mailbox2}  disabledmailbox@4883c000ti,omap4-mailboxH0 mailbox3}  disabledmailbox@4883e000ti,omap4-mailboxH0 mailbox4}  disabledmailbox@48840000ti,omap4-mailboxH0 mailbox5} okaymbox_ipu1_ipc3x  okaymbox_dsp1_ipc3x  okaymailbox@48842000ti,omap4-mailboxH 0 mailbox6} okaymbox_ipu2_ipc3x  okaymbox_dsp2_ipc3x  okaymailbox@48844000ti,omap4-mailboxH@0 mailbox7}  disabledmailbox@48846000ti,omap4-mailboxH`0 mailbox8}  disabledmailbox@4885e000ti,omap4-mailboxH0     mailbox9}  disabledmailbox@48860000ti,omap4-mailboxH0  mailbox10}  disabledmailbox@48862000ti,omap4-mailboxH 0 mailbox11}  disabledmailbox@48864000ti,omap4-mailboxH@0 mailbox12}  disabledmailbox@48802000ti,omap4-mailboxH 0{|}~ mailbox13}  disabledtimer@4ae18000ti,omap5430-timerJ timer1timer@48032000ti,omap5430-timerH  !timer2timer@48034000ti,omap5430-timerH@ "timer3timer@48036000ti,omap5430-timerH` #timer4timer@48820000ti,omap5430-timerH $timer5timer@48822000ti,omap5430-timerH  %timer6timer@48824000ti,omap5430-timerH@ &timer7timer@48826000ti,omap5430-timerH` 'timer8timer@4803e000ti,omap5430-timerH (timer9timer@48086000ti,omap5430-timerH` )timer10timer@48088000ti,omap5430-timerH *timer11timer@48828000ti,omap5430-timerH Stimer13 disabledtimer@4882a000ti,omap5430-timerH Ttimer14 disabledtimer@4882c000ti,omap5430-timerH Utimer15 disabledtimer@4882e000ti,omap5430-timerH Vtimer16 disabledwdt@4ae14000 ti,omap3-wdtJ@ K wd_timer2spinlock@4a0f6000ti,omap4-hwspinlockJ` spinlockdmm@4e000000 ti,omap5-dmmN ldmmi2c@48070000 ti,omap4-i2cH 3i2c1okaydefaulti2c@48072000 ti,omap4-i2cH  4i2c2 disabledi2c@48060000 ti,omap4-i2cH 8i2c3okaydefaulti2c@4807a000 ti,omap4-i2cH 9i2c4okaydefaulttps659038@58 ti,tps659038X&defaulttps659038_pmicti,tps659038-pmicregulatorssmps12Hsmps12W Po'smps3Hsmps3W`o`'smps45Hsmps45W Po'smps6Hsmps6W Po'smps7Hsmps7W Po@'smps8Hsmps8W Po'smps9Hsmps9W2Zo2Z'ldo1Hldo1Ww@o2Z'ldo2Hldo2Ww@ow@'ldo3Hldo3Ww@ow@'ldo4Hldo4Ww@ow@'ldo9Hldo9Wo'ldolnHldolnWw@ow@'ldousbHldousbW2Zo2Z'tps659038_pwr_buttonti,palmas-pwrbutton&9G tps659038_gpioti,palmas-gpio>Nrtc@56emmicro,em3027Vatmel@50 atmel,24c08Pdwm8731@1am wlf,wm8731okayi2c@4807c000 ti,omap4-i2cH 7i2c5 disabledmmc@4809c000ti,omap4-hsmmcH  Nmmc1~n=>stxrx disabledmmc@480b4000ti,omap4-hsmmcH @ Qmmc2n/0stxrxokaydefaultmmc@480ad000ti,omap4-hsmmcH  Ymmc3nMNstxrx disabledmmc@480d1000ti,omap4-hsmmcH  [mmc4n9:stxrx disabledmmu@40d01000ti,dra7-dsp-iommu@  mmu0_dsp1 disabledmmu@40d02000ti,dra7-dsp-iommu@   mmu1_dsp1 disabledmmu@58882000ti,dra7-iommuX   mmu_ipu1 disabledmmu@55082000ti,dra7-iommuU   mmu_ipu2 disabledregulator-abb-mpu ti,abb-v3Habb_mpu $25(J}J}J`J; JXDsetup-addresscontrol-addressint-addressefuse-addressldo-addressE^vH,@vregulator-abb-ivahd ti,abb-v3 Habb_ivahd $25(J~4J~$J`J% J$pDsetup-addresscontrol-addressint-addressefuse-addressldo-addressE@^vH0regulator-abb-dspeve ti,abb-v3 Habb_dspeve $25(J~0J~ J`J% J$lDsetup-addresscontrol-addressint-addressefuse-addressldo-addressE ^vH0regulator-abb-gpu ti,abb-v3Habb_gpu $25(J}J}J`J; JTDsetup-addresscontrol-addressint-addressefuse-addressldo-addressE^vHvspi@48098000ti,omap4-mcspiH  <mcspi1@n#$%&'()* stx0rx0tx1rx1tx2rx2tx3rx3 disabledspi@4809a000ti,omap4-mcspiH  =mcspi2 n+,-.stx0rx0tx1rx1 disabledspi@480b8000ti,omap4-mcspiH  Vmcspi3nstx0rx0 disabledspi@480ba000ti,omap4-mcspiH  +mcspi4nFGstx0rx0 disabledqspi@4b300000ti,dra7xxx-qspiK0\qspi_baseqspi_mmapXqspifck Wokaydefaultlspi_flash@0spansion,m25p80jedec,spi-norlpartition@0uboot partition@c0000uboot environment partition@100000 reservedads7846@0default ti,ads7846`& '7G W9control-phy@4a002374ti,control-phy-pipe3J#tpower sysclkocp2scp@4a090000ti,omap-ocp2scp&J  ocp2scp3phy@4A096000ti,phy-pipe3-sataJ `J ddJ h@phy_rxphy_txpll_ctrlg sysclkrefclkspciephy@4a094000ti,phy-pipe3-pcieJ @J Ddphy_rxphy_txgLMQ4dpll_refdpll_ref_m2wkupclkrefclkdiv-clkphy-divpciephy@4a095000ti,phy-pipe3-pcieJ PJ Tdphy_rxphy_txgLMQ4dpll_refdpll_ref_m2wkupclkrefclkdiv-clkphy-div disabledsata@4a141100snps,dwc-ahciJJ 1 sata-physataokaycontrol-phy@0x4a003c40ti,control-phy-pcieJ<@J<J<4powercontrol_smapcie_pcs sysclkcontrol-pcie@0x4a003c44ti,control-phy-pcieJ