8{(M{L#radxa,rock2-squarerockchip,rk3288&7Radxa Rock 2 Squarechosen=serial2:115200n8aliasesI/ethernet@ff290000S/i2c@ff650000X/i2c@ff140000]/i2c@ff660000b/i2c@ff150000g/i2c@ff160000l/i2c@ff170000q/dwmmc@ff0f0000w/dwmmc@ff0c0000}/dwmmc@ff0d0000/dwmmc@ff0e0000/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000memorymemoryarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12 `@p@ @OOa sB@ ~ ' 9  K 0 !0@>EQWcpu@501cpuarm,cortex-a12 QWcpu@502cpuarm,cortex-a12 QWcpu@503cpuarm,cortex-a12 QWamba simple-bus_dma-controller@ff250000arm,pl330arm,primecell%@fq> apb_pclkQWdma-controller@ff600000arm,pl330arm,primecell`@fq> apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@fq> apb_pclkQMWMreserved-memory_dma-unusable@fe000000oscillator fixed-clockn6xin24mQ W timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H > a timerpclkdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshcр >Drvbiuciuciu-driveciu-sample   @okay!3DVakdefaulty dwmmc@ff0d0000rockchip,rk3288-dw-mshcр >Eswbiuciuciu-driveciu-sample  ! @okay3Vakdefaultydwmmc@ff0e0000rockchip,rk3288-dw-mshcр >Ftxbiuciuciu-driveciu-sample  "@ disableddwmmc@ff0f0000rockchip,rk3288-dw-mshcр >Guybiuciuciu-driveciu-sample  #@okay!Vakdefault ysaradc@ff100000rockchip,saradc $>I[saradcapb_pclk disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi>ARspiclkapb_pclk  txrx ,kdefaulty !" disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi>BSspiclkapb_pclk txrx -kdefaulty#$%& disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi>CTspiclkapb_pclktxrx .kdefaulty'()* disabledi2c@ff140000rockchip,rk3288-i2c >i2c>Mkdefaulty+ disabledi2c@ff150000rockchip,rk3288-i2c ?i2c>Okdefaulty, disabledi2c@ff160000rockchip,rk3288-i2c @i2c>Pkdefaulty- disabledi2c@ff170000rockchip,rk3288-i2c Ai2c>Qkdefaulty.okayQYWYserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7>MUbaudclkapb_pclkkdefaulty/ disabledserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8>NVbaudclkapb_pclkkdefaulty0 disabledserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9>OWbaudclkapb_pclkkdefaulty1okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :>PXbaudclkapb_pclkkdefaulty2 disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;>QYbaudclkapb_pclkkdefaulty3 disabledthermal-zonesreserve_thermal4cpu_thermald4tripscpu_alert0.p:passiveQ5W5cpu_alert1.$:passiveQ6W6cpu_crit._: criticalcooling-mapsmap0E5 Jmap1E6 Jgpu_thermald4tripsgpu_alert0.p:passiveQ7W7gpu_crit._: criticalcooling-mapsmap0E7 Jtsadc@ff280000rockchip,rk3288-tsadc( %>HZtsadcapb_pclk  Ytsadc-apbkinitdefaultsleepy8e9o8ysokayQ4W4ethernet@ff290000rockchip,rk3288-gmac) macirq:8>fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac B Ystmmacethok;input)rgmii2<kdefaulty=> =?M c'u0x0usb@ff500000 generic-ehciP >usbhost@usbokayusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T >otghostA usb2-phy disabledusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X >otgotg@@ B usb2-phy disabledusb@ff5c0000 generic-ehci\ >usbhost disabledi2c@ff650000rockchip,rk3288-i2ce <i2c>LkdefaultyCokayact8846@5aactive-semi,act8846ZD ED"D-D8DregulatorsREG1CVCC_DDRROjOREG2CVCC_IOR2Zj2ZQWREG3CVDD_LOGRB@jB@REG4CVCC_20RjQEWEREG5 CVCCIO_SDR2Zj2ZQWREG6 CVDD10_LCDRB@jB@REG7 CVCCA_CODECR2Zj2ZREG8CVCCA_TPR2Zj2ZREG9 CVCCIO_PMUR2Zj2ZQ<W<REG10CVDD_10RB@jB@REG11CVCC_18Rw@jw@QWREG12 CVCC18_LCDRw@jw@syr827@40silergy,syr827@,Cvdd_cpuR Pjp@DQWsyr828@41silergy,syr828A,R PjpCvdd_gpu@Dhym8563@51haoyu,hym8563Qxin32k&FkdefaultyGQgWgi2c@ff660000rockchip,rk3288-i2cf =i2c>NkdefaultyH disabledpwm@ff680000rockchip,rk3288-pwmhkdefaultyI>^pwm disabledpwm@ff680010rockchip,rk3288-pwmhkdefaultyJ>^pwm disabledpwm@ff680020rockchip,rk3288-pwmh kdefaultyK>^pwm disabledpwm@ff680030rockchip,rk3288-pwmh0kdefaultyL>^pwm disabledbus_intmem@ff700000 mmio-sramp _psmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsQWpower-controller!rockchip,rk3288-power-controller h QPWPpd_vio >chgfdehilkjpd_hevc >oppd_video >pd_gpu >syscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv: Hjk$-#gׄeрxhрxhQWsyscon@ff770000rockchip,rk3288-grfsysconwQ:W:watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt>p Ookaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdifB hclkmclk>TMtx UkdefaultyN:okayQeWei2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s UMMtxrxi2s_hclki2s_clk>RkdefaultyOSn disabledcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 >}aclkhclksclkapb_pclk  Ycrypto-rstokayvop@ff930000rockchip,rk3288-vop >aclk_vopdclk_vophclk_vopP  def YaxiahbdclkQokayportQ W endpoint@0RQZWZendpoint@2SQWWWiommu@ff930300rockchip,iommu  vopb_mmuP okayQQWQvop@ff940000rockchip,rk3288-vop >aclk_vopdclk_vophclk_vopP   YaxiahbdclkTokayportQ W endpoint@0UQ[W[endpoint@2VQXWXiommu@ff940300rockchip,iommu  vopl_mmuP okayQTWTmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ S>~d refpclk: disabledportsportendpoint@0WQSWSendpoint@1XQVWVhdmi@ff980000rockchip,rk3288-dw-hdmi: g>hm iahbisfrP okayYportsportendpoint@0ZQRWRendpoint@1[QUWUinterrupt-controller@ffc01000 arm,gic-400  @ `   QWefuse@ffb40000rockchip,rockchip-efuse >q pclk_efusecpu_leakage@17phyrockchip,rk3288-usb-phy:okayusb-phy0 >]phyclkQBWBusb-phy14>^phyclkQ@W@usb-phy2H>_phyclkQAWApinctrlrockchip,rk3288-pinctrl:_gpio0@ff750000rockchip,gpio-banku Q>@QFWFgpio1@ff780000rockchip,gpio-bankx R>Agpio2@ff790000rockchip,gpio-banky S>Bgpio3@ff7a0000rockchip,gpio-bankz T>CQaWagpio4@ff7b0000rockchip,gpio-bank{ U>DQ?W?gpio5@ff7c0000rockchip,gpio-bank| V>Egpio6@ff7d0000rockchip,gpio-bank} W>Fgpio7@ff7e0000rockchip,gpio-bank~ X>GQbWbgpio8@ff7f0000rockchip,gpio-bank Y>HQcWchdmihdmi-ddc \\pcfg-pull-up!Q]W]pcfg-pull-down.pcfg-pull-none=Q\W\pcfg-pull-none-12ma=J Q^W^sleepglobal-pwroff\ddrio-pwroff\ddr0-retention]ddr1-retention]i2c0i2c0-xfer \\QCWCi2c1i2c1-xfer \\Q+W+i2c2i2c2-xfer  \ \QHWHi2c3i2c3-xfer \\Q,W,i2c4i2c4-xfer \\Q-W-i2c5i2c5-xfer \\Q.W.i2s0i2s0-bus`\\\\\\QOWOsdmmcsdmmc-clk\Q W sdmmc-cmd]Q W sdmmc-cd]QWsdmmc-bus1]sdmmc-bus4@]]]]QWsdmmc-pwr \QjWjsdio0sdio0-bus1]sdio0-bus4@]]]]QWsdio0-cmd]QWsdio0-clk\QWsdio0-cd]sdio0-wp]sdio0-pwr]sdio0-bkpwr]sdio0-int]QWsdio1sdio1-bus1]sdio1-bus4@]]]]sdio1-cd]sdio1-wp]sdio1-bkpwr]sdio1-int]sdio1-cmd]sdio1-clk\sdio1-pwr ]emmcemmc-clk\QWemmc-cmd]QWemmc-pwr ]emmc-bus1]emmc-bus4@]]]]emmc-bus8]]]]]]]]QWemmc-reset \Q`W`spi0spi0-clk ]QWspi0-cs0 ]Q"W"spi0-tx]Q W spi0-rx]Q!W!spi0-cs1]spi1spi1-clk ]Q#W#spi1-cs0 ]Q&W&spi1-rx]Q%W%spi1-tx]Q$W$spi2spi2-cs1]spi2-clk]Q'W'spi2-cs0]Q*W*spi2-rx]Q)W)spi2-tx ]Q(W(uart0uart0-xfer ]\Q/W/uart0-cts]uart0-rts\uart1uart1-xfer ] \Q0W0uart1-cts ]uart1-rts \uart2uart2-xfer ]\Q1W1uart3uart3-xfer ]\Q2W2uart3-cts ]uart3-rts \uart4uart4-xfer  ] \Q3W3uart4-cts]uart4-rts\tsadcotp-gpio \Q8W8otp-out \Q9W9pwm0pwm0-pin\QIWIpwm1pwm1-pin\QJWJpwm2pwm2-pin\QKWKpwm3pwm3-pin\QLWLgmacrgmii-pins\\\\^^^^\\\ ^^\\Q=W=rmii-pins\\\\\\\\\\phy-rst_Q>W>spdifspdif-tx \QNWNpcfg-output-highYQ_W_irir-int]QdWdpmicpmic-int]QGWGusbhost-vbus-drv\QiWisdiowifi-enable\QhWhemmc-pwrseqmmc-pwrseq-emmcy`kdefault ea QWexternal-gmac-clock fixed-clocksY@ ext_gmacQ;W;io-domains"rockchip,rk3288-io-voltage-domain:q~<<flash-regulatorregulator-fixedCvcc_sysRw@jw@QWvsys-regulatorregulator-fixedCvcc_sysRLK@jLK@QDWDgpio-leds gpio-ledsheartbeat kbrock2:green:state1 heartbeatmmc kF rock2:blue:state2mmc0ir-receivergpio-ir-receiver kckdefaultydsoundsimple-audio-cardSPDIFsimple-audio-card,dai-link@1cpu0ecodec0fspdif-outlinux,spdif-ditBQfWfsdio-pwrseqmmc-pwrseq-simple>g ext_clockkdefaultyh e?QWvcc-host-regulatorregulator-fixed: HFkdefaultyi Cvcc_hostsdmmc-regulatorregulator-fixed Hb kdefaultyjCvcc_sdR2Zj2ZQW #address-cells#size-cellscompatibleinterrupt-parentmodelstdout-pathethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2device_typereginterruptsinterrupt-affinityenable-methodrockchip,pmuresetsoperating-points#cooling-cellsclock-latencyclockscpu0-supplylinux,phandleranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredportsclock-freq-min-maxfifo-depthbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wpnum-slotspinctrl-namespinctrl-0vmmc-supplyvqmmc-supplycap-sdio-irqmmc-pwrseqnon-removable#io-channel-cellsdmasdma-namesreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfassigned-clocksassigned-clock-parentsclock_in_outphy-modephy-supplysnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usrx_delaytx_delayphysphy-namesdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmasystem-power-controllerinl1-supplyinl2-supplyinl3-supplyvp1-supplyvp2-supplyvp3-supplyvp4-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onfcs,suspend-voltage-selectorregulator-boot-onregulator-enable-ramp-delayregulator-ramp-delayvin-supply#pwm-cells#power-domain-cells#reset-cellsassigned-clock-rates#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channelspower-domainsiommusremote-endpoint#iommu-cellsddc-i2c-businterrupt-controller#interrupt-cells#phy-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highreset-gpiosaudio-supplybb-supplydvp-supplyflash0-supplyflash1-supplygpio30-supplygpio1830lcdc-supplysdcard-supplywifi-supplystartup-delay-uslabellinux,default-triggersimple-audio-card,namesound-daienable-active-high