%8{@({Kgoogle,veyron-brain-rev0google,veyron-braingoogle,veyronrockchip,rk3288& 7Google Brainchosenaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000memorymemoryarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12`@p@ @OOa sB@ ~ ' 9  K 0 $@29EKcpu@501cpuarm,cortex-a12EKcpu@502cpuarm,cortex-a12EKcpu@503cpuarm,cortex-a12EKamba simple-busSdma-controller@ff250000arm,pl330arm,primecell%@Ze2 apb_pclkEKdma-controller@ff600000arm,pl330arm,primecell`@Ze2 apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@Ze2 apb_pclkEDKDreserved-memorySdma-unusable@fe000000oscillator fixed-clockn6xin24mE K timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 2 a timerpclkdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshcр 2Drvbiuciuciu-driveciu-sample  @ disableddwmmc@ff0d0000rockchip,rk3288-dw-mshcр 2Eswbiuciuciu-driveciu-sample ! @okay 0=S ^lvdefault  dwmmc@ff0e0000rockchip,rk3288-dw-mshcр 2Ftxbiuciuciu-driveciu-sample "@ disableddwmmc@ff0f0000rockchip,rk3288-dw-mshcр 2Guybiuciuciu-driveciu-sample #@okay  S^lvdefault saradc@ff100000rockchip,saradc $&2I[saradcapb_pclk disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi2ARspiclkapb_pclk8  =txrx ,vdefault disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi2BSspiclkapb_pclk8 =txrx -vdefault disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi2CTspiclkapb_pclk8=txrx .vdefault !"okayG i2c@ff140000rockchip,rk3288-i2c >i2c2Mvdefault#okayZ2rdtpm@20infineon,slb9645tt i2c@ff150000rockchip,rk3288-i2c ?i2c2Ovdefault$ disabledi2c@ff160000rockchip,rk3288-i2c @i2c2Pvdefault%okayZ2r,i2c@ff170000rockchip,rk3288-i2c Ai2c2Qvdefault&okayZ,rEPKPserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 72MUbaudclkapb_pclkvdefault '()okayMlserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 82NVbaudclkapb_pclkvdefault*okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 92OWbaudclkapb_pclkvdefault+okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :2PXbaudclkapb_pclkvdefault, disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;2QYbaudclkapb_pclkvdefault- disabledthermal-zonesreserve_thermal.cpu_thermald.tripscpu_alert0ppassiveE/K/cpu_alert1$passiveE0K0cpu_crit_ criticalcooling-mapsmap0(/ -map1(0 -gpu_thermald.tripsgpu_alert0ppassiveE1K1gpu_crit_ criticalcooling-mapsmap0(1 -tsadc@ff280000rockchip,rk3288-tsadc( %2HZtsadcapb_pclk  >E^K^regulatorsDCDC_REG1vdd_arm& q> VqEKregulator-state-memkDCDC_REG2vdd_gpu& 5>Vqregulator-state-memB@DCDC_REG3 vcc135_ddrregulator-state-memDCDC_REG4vcc_18&w@>w@EKregulator-state-memw@LDO_REG3vdd_10&B@>B@regulator-state-memB@LDO_REG7 vdd10_lcd&B@>B@regulator-state-memkSWITCH_REG1 vcc33_lcdE]K]regulator-state-memkSWITCH_REG2 vcc18_hdmii2c@ff660000rockchip,rk3288-i2cf =i2c2Nvdefault?okayZ2r pwm@ff680000rockchip,rk3288-pwmhvdefault@2^pwm disabledpwm@ff680010rockchip,rk3288-pwmhvdefaultA2^pwmokaypwm@ff680020rockchip,rk3288-pwmh vdefaultB2^pwm disabledpwm@ff680030rockchip,rk3288-pwmh0vdefaultC2^pwm disabledbus_intmem@ff700000 mmio-sramp Spsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsEKpower-controller!rockchip,rk3288-power-controllerh? EGKGpd_vio 2chgfdehilkjpd_hevc 2oppd_video 2pd_gpu 2syscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv4Hjk$#gׄeрxhрxhEKsyscon@ff770000rockchip,rk3288-grfsysconwE4K4watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt2p Ookaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif hclkmclk2T8D=tx UvdefaultE4 disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s U8DD=txrxi2s_hclki2s_clk2RvdefaultF/ disabledcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 2}aclkhclksclkapb_pclk K>gpio8@ff7f0000rockchip,gpio-bank Y2Hhdmihdmi-ddc TTvcc50-hdmi-enTEcKcpcfg-pull-upEUKUpcfg-pull-downEXKXpcfg-pull-noneETKTpcfg-pull-none-12ma EWKWsleepglobal-pwroffTESKSddrio-pwroffTddr0-retentionUddr1-retentionUi2c0i2c0-xfer TTE8K8i2c1i2c1-xfer TTE#K#i2c2i2c2-xfer  T TE?K?i2c3i2c3-xfer TTE$K$i2c4i2c4-xfer TTE%K%i2c5i2c5-xfer TTE&K&i2s0i2s0-bus`TTTTTTEFKFsdmmcsdmmc-clkTsdmmc-cmdUsdmmc-cdUsdmmc-bus1Usdmmc-bus4@UUUUsdio0sdio0-bus1Usdio0-bus4@VVVVEKsdio0-cmdVEKsdio0-clkVE K sdio0-cdUsdio0-wpUsdio0-pwrUsdio0-bkpwrUsdio0-intUwifienable-hTE`K`bt-enable-lTE_K_sdio1sdio1-bus1Usdio1-bus4@UUUUsdio1-cdUsdio1-wpUsdio1-bkpwrUsdio1-intUsdio1-cmdUsdio1-clkTsdio1-pwr Uemmcemmc-clkVEKemmc-cmdVEKemmc-pwr Uemmc-bus1Uemmc-bus4@UUUUemmc-bus8VVVVVVVVEKemmc-reset TE[K[spi0spi0-clk UEKspi0-cs0 UEKspi0-txUEKspi0-rxUEKspi0-cs1Uspi1spi1-clk UEKspi1-cs0 UEKspi1-rxUEKspi1-txUEKspi2spi2-cs1Uspi2-clkUEKspi2-cs0UE"K"spi2-rxUE!K!spi2-tx UE K uart0uart0-xfer UTE'K'uart0-ctsUE(K(uart0-rtsTE)K)uart1uart1-xfer U TE*K*uart1-cts Uuart1-rts Tuart2uart2-xfer UTE+K+uart3uart3-xfer UTE,K,uart3-cts Uuart3-rts Tuart4uart4-xfer  U TE-K-uart4-ctsUuart4-rtsTtsadcotp-gpio TE2K2otp-out TE3K3pwm0pwm0-pinTE@K@pwm1pwm1-pinTEAKApwm2pwm2-pinTEBKBpwm3pwm3-pinTECKCgmacrgmii-pinsTTTTWWWWTTT WWTTrmii-pinsTTTTTTTTTTspdifspdif-tx TEEKEpcfg-pull-none-drv-8ma EVKVpcfg-pull-up-drv-8ma pcfg-output-highpcfg-output-low&buttonspwr-key-lUEYKYpmicpmic-int-lUE:K:dvs-1 XE;K;dvs-2XE<K<rebootap-warm-reset-h TEZKZrecovery-switchrec-mode-l Utpmtpm-int-hTwrite-protectfw-wp-apTusb-hostusb2-pwr-en TEdKdgpio-keys gpio-keysvdefaultYpower1Power 97tBdwgpio-restart gpio-restart 9 vdefaultZTemmc-pwrseqmmc-pwrseq-emmc[vdefault ]\ EKio-domains"rockchip,rk3288-io-voltage-domain4i=s~==]sdio-pwrseqmmc-pwrseq-simple2^ ext_clockvdefault_` ]aE K vcc-5vregulator-fixedvcc_5v&LK@>LK@EbKbvcc33-sysregulator-fixed vcc33_sys&2Z>2ZbEKvcc50-hdmiregulator-fixed vcc50_hdmib >vdefaultcvcc33_ioregulator-fixed vcc33_ioE=K=vcc5-host2-regulatorregulator-fixed 9 vdefaultd vcc5_host2 #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2device_typereginterruptsinterrupt-affinityenable-methodrockchip,pmuresetsoperating-points#cooling-cellsclock-latencyclockscpu0-supplylinux,phandleranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredportsclock-freq-min-maxfifo-depthbroken-cdbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablenum-slotspinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplycap-mmc-highspeedrockchip,default-sample-phasedisable-wpmmc-hs200-1_8v#io-channel-cellsdmasdma-namesrx-sample-delay-nsi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedreg-shiftreg-io-widthassigned-clocksassigned-clock-ratespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfphysphy-namesneeds-reset-on-resumedr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmaassigned-clock-parentsrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplydvs-gpiosregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltregulator-suspend-mem-disabled#pwm-cells#power-domain-cells#reset-cells#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channelspower-domainsiommusremote-endpoint#iommu-cellsddc-i2c-businterrupt-controller#interrupt-cells#phy-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowlabellinux,codedebounce-intervalpriorityreset-gpiosbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyvin-supplyenable-active-highgpio