8( google,veyron-jerry-rev7google,veyron-jerry-rev6google,veyron-jerry-rev5google,veyron-jerry-rev4google,veyron-jerry-rev3google,veyron-jerrygoogle,veyronrockchip,rk3288& 7Google Jerrychosenaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/spi@ff110000/ec@0/i2c-tunnelmemorymemoryarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12` @p@ @OOa sB@ ~ ' 9  K 0 *@8?KQcpu@501cpuarm,cortex-a12KQcpu@502cpuarm,cortex-a12KQcpu@503cpuarm,cortex-a12KQamba simple-busYdma-controller@ff250000arm,pl330arm,primecell%@`k8 apb_pclkKQdma-controller@ff600000arm,pl330arm,primecell`@`k8 apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@`k8 apb_pclkKLQLreserved-memoryYdma-unusable@fe000000oscillator fixed-clockn6xin24mK Q timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 8 a timerpclkdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshcр 8Drvbiuciuciu-driveciu-sample  @okay-> P YZw defaultdwmmc@ff0d0000rockchip,rk3288-dw-mshcр 8Eswbiuciuciu-driveciu-sample ! @okay- *wdefault dwmmc@ff0e0000rockchip,rk3288-dw-mshcр 8Ftxbiuciuciu-driveciu-sample "@ disableddwmmc@ff0f0000rockchip,rk3288-dw-mshcр 8Guybiuciuciu-driveciu-sample #@okayY8*wdefault saradc@ff100000rockchip,saradc $G8I[saradcapb_pclk disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi8ARspiclkapb_pclkY  ^txrx ,default !"okayec@0google,cros-ec-spih& default#-i2c-tunnelgoogle,cros-ec-i2c-tunnelsbs-battery@bsbs,sbs-battery keyboard-controllergoogle,cros-ec-keyb @};0DY1 d>"A#( C  \=@V B |)<?   + ^a !%$' & + ,./-32*5 4 9    8 l j6  g ispi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi8BSspiclkapb_pclkY ^txrx -default$%&' disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi8CTspiclkapb_pclkY^txrx .default()*+okay i2c@ff140000rockchip,rk3288-i2c >i2c8Mdefault,okay/2Gdtpm@20infineon,slb9645tt ^i2c@ff150000rockchip,rk3288-i2c ?i2c8Odefault- disabledi2c@ff160000rockchip,rk3288-i2c @i2c8Pdefault./okay/2G,trackpad@15elan,ekth3000& v0trackpad@2c hid-over-i2c& , v0i2c@ff170000rockchip,rk3288-i2c Ai2c8Qdefault1okay/,GKXQXserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 78MUbaudclkapb_pclkdefault 234okayMlserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 88NVbaudclkapb_pclkdefault5okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 98OWbaudclkapb_pclkdefault6okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :8PXbaudclkapb_pclkdefault7 disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;8QYbaudclkapb_pclkdefault8 disabledthermal-zonesreserve_thermal9cpu_thermald9tripscpu_alert0ppassiveK:Q:cpu_alert1$passiveK;Q;cpu_crit_ criticalcooling-mapsmap0%: *map1%; *gpu_thermald9tripsgpu_alert0ppassiveK<Q<gpu_crit_ criticalcooling-mapsmap0%< *tsadc@ff280000rockchip,rk3288-tsadc( %8HZtsadcapb_pclk 9tsadc-apbinitdefaultsleep=E>O=YosokayK9Q9ethernet@ff290000rockchip,rk3288-gmac) macirq?88fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB 9stmmaceth disabledusb@ff500000 generic-ehciP 8usbhost@usbokayusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 8otghostA usb2-phyokayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 8otghost#@@ 2B usb2-phyokayz<Busb@ff5c0000 generic-ehci\ 8usbhost disabledi2c@ff650000rockchip,rk3288-i2ce <i2c8LdefaultCokay/2Gdpmic@1brockchip,rk808xin32kwifibt_32kin&DdefaultEStF0FFKkQkregulatorsDCDC_REG1vdd_arm 0 qH `qKQregulator-state-memuDCDC_REG2vdd_gpu 0 5H`qregulator-state-memB@DCDC_REG3 vcc135_ddr regulator-state-memDCDC_REG4vcc_18 0w@Hw@KQregulator-state-memw@LDO_REG1 vcc33_io 02ZH2ZK0Q0regulator-state-mem2ZLDO_REG3vdd_10 0B@HB@regulator-state-memB@LDO_REG7vdd10_lcd_pwren_h 0&%H&%regulator-state-memuSWITCH_REG1 vcc33_lcd KjQjregulator-state-memuLDO_REG4 vccio_sd0w@H2ZKQregulator-state-memuLDO_REG5 vcc33_sd02ZH2ZK Q regulator-state-memuLDO_REG8 vcc33_ccd 02ZH2Zregulator-state-mem2ZLDO_REG2mic_vcc 0w@Hw@regulator-state-memui2c@ff660000rockchip,rk3288-i2cf =i2c8NdefaultGokay/2G pwm@ff680000rockchip,rk3288-pwmhdefaultH8^pwm disabledpwm@ff680010rockchip,rk3288-pwmhdefaultI8^pwmokaypwm@ff680020rockchip,rk3288-pwmh defaultJ8^pwm disabledpwm@ff680030rockchip,rk3288-pwmh0defaultK8^pwm disabledbus_intmem@ff700000 mmio-sramp Ypsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsKQpower-controller!rockchip,rk3288-power-controllerh< KOQOpd_vio 8chgfdehilkjpd_hevc 8oppd_video 8pd_gpu 8syscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv?Hjk$#gׄeрxhрxhKQsyscon@ff770000rockchip,rk3288-grfsysconwK?Q?watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt8p Ookaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif hclkmclk8TYL^tx UdefaultM? disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s UYLL^txrxi2s_hclki2s_clk8RdefaultN disabledcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 8}aclkhclksclkapb_pclk 9crypto-rstokayvop@ff930000rockchip,rk3288-vop 8aclk_vopdclk_vophclk_vop4O def 9axiahbdclkBPokayportK Q endpoint@0IQKYQYendpoint@2IRKVQViommu@ff930300rockchip,iommu  vopb_mmu4O YokayKPQPvop@ff940000rockchip,rk3288-vop 8aclk_vopdclk_vophclk_vop4O  9axiahbdclkBS disabledportK Q endpoint@0ITKZQZendpoint@2IUKWQWiommu@ff940300rockchip,iommu  vopl_mmu4O Y disabledKSQSmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ S8~d refpclk? disabledportsportendpoint@0IVKRQRendpoint@1IWKUQUhdmi@ff980000rockchip,rk3288-dw-hdmi? g8hm iahbisfr4O okayfXportsportendpoint@0IYKQQQendpoint@1IZKTQTinterrupt-controller@ffc01000 arm,gic-400r  @ `   KQefuse@ffb40000rockchip,rockchip-efuse 8q pclk_efusecpu_leakage@17phyrockchip,rk3288-usb-phy?okayusb-phy0 8]phyclkKBQBusb-phy148^phyclkK@Q@usb-phy2H8_phyclkKAQApinctrlrockchip,rk3288-pinctrl?Ydefaultsleep[\E[]gpio0@ff750000rockchip,gpio-banku Q8@rKDQDgpio1@ff780000rockchip,gpio-bankx R8Argpio2@ff790000rockchip,gpio-banky S8BrKiQigpio3@ff7a0000rockchip,gpio-bankz T8Crgpio4@ff7b0000rockchip,gpio-bank{ U8DrKnQngpio5@ff7c0000rockchip,gpio-bank| V8ErKqQqgpio6@ff7d0000rockchip,gpio-bank} W8Frgpio7@ff7e0000rockchip,gpio-bank~ X8GrK Q gpio8@ff7f0000rockchip,gpio-bank Y8Hrhdmihdmi-ddc ^^vcc50-hdmi-en^KrQrpcfg-pull-upK_Q_pcfg-pull-downKbQbpcfg-pull-noneK^Q^pcfg-pull-none-12ma KaQasleepglobal-pwroff^K[Q[ddrio-pwroff^ddr0-retention_ddr1-retention_i2c0i2c0-xfer ^^KCQCi2c1i2c1-xfer ^^K,Q,i2c2i2c2-xfer  ^ ^KGQGi2c3i2c3-xfer ^^K-Q-i2c4i2c4-xfer ^^K.Q.i2c5i2c5-xfer ^^K1Q1i2s0i2s0-bus`^^^^^^KNQNsdmmcsdmmc-clk`KQsdmmc-cmd`KQsdmmc-cd_sdmmc-bus1_sdmmc-bus4@````KQsdmmc-cd-disabled^KQsdmmc-cd-gpio^KQsdio0sdio0-bus1_sdio0-bus4@````KQsdio0-cmd`KQsdio0-clk`KQsdio0-cd_sdio0-wp_sdio0-pwr_sdio0-bkpwr_sdio0-int_wifienable-h^KmQmbt-enable-l^KlQlsdio1sdio1-bus1_sdio1-bus4@____sdio1-cd_sdio1-wp_sdio1-bkpwr_sdio1-int_sdio1-cmd_sdio1-clk^sdio1-pwr _emmcemmc-clk`KQemmc-cmd`KQemmc-pwr _emmc-bus1_emmc-bus4@____emmc-bus8````````KQemmc-reset ^KhQhspi0spi0-clk _KQspi0-cs0 _K"Q"spi0-tx_K Q spi0-rx_K!Q!spi0-cs1_spi1spi1-clk _K$Q$spi1-cs0 _K'Q'spi1-rx_K&Q&spi1-tx_K%Q%spi2spi2-cs1_spi2-clk_K(Q(spi2-cs0_K+Q+spi2-rx_K*Q*spi2-tx _K)Q)uart0uart0-xfer _^K2Q2uart0-cts_K3Q3uart0-rts^K4Q4uart1uart1-xfer _ ^K5Q5uart1-cts _uart1-rts ^uart2uart2-xfer _^K6Q6uart3uart3-xfer _^K7Q7uart3-cts _uart3-rts ^uart4uart4-xfer  _ ^K8Q8uart4-cts_uart4-rts^tsadcotp-gpio ^K=Q=otp-out ^K>Q>pwm0pwm0-pin^KHQHpwm1pwm1-pin^KIQIpwm2pwm2-pin^KJQJpwm3pwm3-pin^KKQKgmacrgmii-pins^^^^aaaa^^^ aa^^rmii-pins^^^^^^^^^^spdifspdif-tx ^KMQMpcfg-pull-none-drv-8maK`Q`pcfg-pull-up-drv-8mapcfg-output-high KdQdpcfg-output-low KcQcbuttonspwr-key-l_KeQeap-lid-int-l_KfQfpmicpmic-int-l_KEQEdvs-1 bdvs-2brebootap-warm-reset-h ^KgQgrecovery-switchrec-mode-l _tpmtpm-int-h^write-protectfw-wp-ap^chargerac-present-ap_KsQscros-ecec-int^K#Q#suspendsuspend-l-wakecK\Q\suspend-l-sleepdK]Q]trackpadtrackpad-int_K/Q/usb-hosthost1-pwr-en ^KtQtusbotg-pwren-h ^KuQubacklightbl_pwr_en ^KxQxbuck-5vdrv-5v^KpQplcdlcd-en^KvQvavdd-1v8-disp-en ^KwQwgpio-keys gpio-keysdefaultefpower Power SD "t -dlid Lid SD " ? -gpio-restart gpio-restart SD defaultg Pemmc-pwrseqmmc-pwrseq-emmchdefault Yi KQio-domains"rockchip,rk3288-io-voltage-domain? e0 o z 0 0 j  sdio-pwrseqmmc-pwrseq-simple8k ext_clockdefaultlm YnKQvcc-5vregulator-fixedvcc_5v 0LK@HLK@ o  defaultpKFQFvcc33-sysregulator-fixed vcc33_sys 02ZH2Z oKQvcc50-hdmiregulator-fixed vcc50_hdmi  F  qdefaultrgpio-charger gpio-charger mains SDdefaultsvccsysregulator-fixedvccsys KoQovcc5-host1-regulatorregulator-fixed  D defaultt vcc5_host1 vcc5v-otg-regulatorregulator-fixed  D defaultu vcc5_host2 panel-regulatorregulator-fixed  defaultvpanel_regulator vcc18-lcdregulator-fixed  i defaultw vcc18_lcd  backlight-regulatorregulator-fixed  i defaultxbacklight_regulator  : #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2i2c20device_typereginterruptsinterrupt-affinityenable-methodrockchip,pmuresetsoperating-points#cooling-cellsclock-latencyclockscpu0-supplylinux,phandleranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredportsclock-freq-min-maxfifo-depthbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaycd-gpiosrockchip,default-sample-phasenum-slotssd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplydisable-wppinctrl-namespinctrl-0broken-cdcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablemmc-hs200-1_8v#io-channel-cellsdmasdma-namesgoogle,cros-ec-spi-pre-delayspi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymaprx-sample-delay-nsi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedvcc-supplywakeup-sourcehid-descr-addrreg-shiftreg-io-widthassigned-clocksassigned-clock-ratespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfphysphy-namesneeds-reset-on-resumedr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmaassigned-clock-parentsrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplyvcc9-supplyvcc11-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cells#reset-cells#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channelspower-domainsiommusremote-endpoint#iommu-cellsddc-i2c-businterrupt-controller#interrupt-cells#phy-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowlabellinux,codedebounce-intervallinux,input-typepriorityreset-gpiosbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplysdcard-supplyvin-supplyenable-active-highgpiocharger-typestartup-delay-us