8}(}tgoogle,veyron-mickey-rev8google,veyron-mickey-rev7google,veyron-mickey-rev6google,veyron-mickey-rev5google,veyron-mickey-rev4google,veyron-mickey-rev3google,veyron-mickey-rev2google,veyron-mickey-rev1google,veyron-mickey-rev0google,veyron-mickeygoogle,veyronrockchip,rk3288&7Google Mickeychosenaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000memorymemoryarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12`@p@ @OOa sB@ ~ ' 9  K 0 $@29EKcpu@501cpuarm,cortex-a12EKcpu@502cpuarm,cortex-a12EKcpu@503cpuarm,cortex-a12EKamba simple-busSdma-controller@ff250000arm,pl330arm,primecell%@Ze2 apb_pclkEKdma-controller@ff600000arm,pl330arm,primecell`@Ze2 apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@Ze2 apb_pclkEGKGreserved-memorySdma-unusable@fe000000oscillator fixed-clockn6xin24mE K timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 2 a timerpclkdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshcр 2Drvbiuciuciu-driveciu-sample  @ disableddwmmc@ff0d0000rockchip,rk3288-dw-mshcр 2Eswbiuciuciu-driveciu-sample ! @okay 0=S ^lvdefault  dwmmc@ff0e0000rockchip,rk3288-dw-mshcр 2Ftxbiuciuciu-driveciu-sample "@ disableddwmmc@ff0f0000rockchip,rk3288-dw-mshcр 2Guybiuciuciu-driveciu-sample #@okay  S^lvdefault saradc@ff100000rockchip,saradc $2I[saradcapb_pclk disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi2ARspiclkapb_pclk)  .txrx ,vdefault disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi2BSspiclkapb_pclk) .txrx -vdefault disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi2CTspiclkapb_pclk).txrx .vdefault !"okay8 i2c@ff140000rockchip,rk3288-i2c >i2c2Mvdefault#okayK2cdtpm@20infineon,slb9645tt zi2c@ff150000rockchip,rk3288-i2c ?i2c2Ovdefault$ disabledi2c@ff160000rockchip,rk3288-i2c @i2c2Pvdefault% disabledK2c,i2c@ff170000rockchip,rk3288-i2c Ai2c2Qvdefault&okayK,cESKSserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 72MUbaudclkapb_pclkvdefault '()okayMlserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 82NVbaudclkapb_pclkvdefault*okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 92OWbaudclkapb_pclkvdefault+okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :2PXbaudclkapb_pclkvdefault, disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;2QYbaudclkapb_pclkvdefault- disabledthermal-zonesreserve_thermal.cpu_thermald.tripscpu_crit_ criticalcpu_alert_almost_warmpassivecpu_alert_warmpassiveE/K/cpu_alert_almost_hot8passiveE0K0cpu_alert_hot@PpassiveE1K1cpu_alert_hotterH passiveE2K2cpu_alert_very_hotLpassiveE3K3cooling-mapscpu_warm_limit_cpu/ cpu_almost_hot_limit_cpu0 cpu_hot_limit_cpu1 cpu_hotter_limit_cpu2 cpu_very_hot_limit_cpu3 gpu_thermald.tripsgpu_alert0ppassiveE4K4gpu_crit_ criticalcooling-mapsmap04 tsadc@ff280000rockchip,rk3288-tsadc( %2HZtsadcapb_pclk -tsadc-apbvinitdefaultsleep596C5McsokayzE.K.ethernet@ff290000rockchip,rk3288-gmac) macirq782fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB -stmmaceth disabledusb@ff500000 generic-ehciP 2usbhost8usb disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 2otghost9 usb2-phy disabledusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 2otghost@@ &: usb2-phyokayz0:usb@ff5c0000 generic-ehci\ 2usbhost disabledi2c@ff650000rockchip,rk3288-i2ce <i2c2Lvdefault;okayK2cdpmic@1brockchip,rk808xin32kwifibt_32kin&<vdefault =>?Ghv@A AEaKaregulatorsDCDC_REG1vdd_arm q/ GqEKregulator-state-mem\DCDC_REG2vdd_gpu 5/Gqregulator-state-memuB@DCDC_REG3 vcc135_ddrregulator-state-memuDCDC_REG4vcc_18w@/w@EKregulator-state-memuw@LDO_REG3vdd_10B@/B@regulator-state-memuB@LDO_REG7 vdd10_lcdB@/B@SWITCH_REG1 vcc33_lcdE`K`regulator-state-mem\LDO_REG8w@/w@ vcc18_lcdi2c@ff660000rockchip,rk3288-i2cf =i2c2NvdefaultB disabledK2c pwm@ff680000rockchip,rk3288-pwmhvdefaultC2^pwm disabledpwm@ff680010rockchip,rk3288-pwmhvdefaultD2^pwmokaypwm@ff680020rockchip,rk3288-pwmh vdefaultE2^pwm disabledpwm@ff680030rockchip,rk3288-pwmh0vdefaultF2^pwm disabledbus_intmem@ff700000 mmio-sramp Spsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsEKpower-controller!rockchip,rk3288-power-controllerh0 EJKJpd_vio 2chgfdehilkjpd_hevc 2oppd_video 2pd_gpu 2syscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv7Hjk$#gׄeрxhрxhEKsyscon@ff770000rockchip,rk3288-grfsysconwE7K7watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt2p Ookaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif hclkmclk2T)G.tx UvdefaultH7 disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s U)GG.txrxi2s_hclki2s_clki2s_clk_out2RqvdefaultI okaycypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 2}aclkhclksclkapb_pclk -crypto-rstokayvop@ff930000rockchip,rk3288-vop 2aclk_vopdclk_vophclk_vop:J def -axiahbdclkHKokayportE K endpoint@0OLETKTendpoint@2OMEQKQiommu@ff930300rockchip,iommu  vopb_mmu:J _okayEKKKvop@ff940000rockchip,rk3288-vop 2aclk_vopdclk_vophclk_vop:J  -axiahbdclkHN disabledportE K endpoint@0OOEUKUendpoint@2OPERKRiommu@ff940300rockchip,iommu  vopl_mmu:J _ disabledENKNmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ S2~d refpclk7 disabledportsportendpoint@0OQEMKMendpoint@1OREPKPhdmi@ff980000rockchip,rk3288-dw-hdmi7 g2hm iahbisfr:J okaylSportsportendpoint@0OTELKLendpoint@1OUEOKOinterrupt-controller@ffc01000 arm,gic-400x  @ `   EKefuse@ffb40000rockchip,rockchip-efuse 2q pclk_efusecpu_leakage@17phyrockchip,rk3288-usb-phy7okayusb-phy0 2]phyclkE:K:usb-phy142^phyclkE8K8usb-phy2H2_phyclkE9K9pinctrlrockchip,rk3288-pinctrl7SvdefaultsleepV9Vgpio0@ff750000rockchip,gpio-banku Q2@xE<K<gpio1@ff780000rockchip,gpio-bankx R2Axgpio2@ff790000rockchip,gpio-banky S2BxE_K_gpio3@ff7a0000rockchip,gpio-bankz T2Cxgpio4@ff7b0000rockchip,gpio-bank{ U2DxEdKdgpio5@ff7c0000rockchip,gpio-bank| V2Exgpio6@ff7d0000rockchip,gpio-bank} W2Fxgpio7@ff7e0000rockchip,gpio-bank~ X2GxEAKAgpio8@ff7f0000rockchip,gpio-bank Y2Hxhdmihdmi-ddc WWpower-hdmi-on WEfKfpcfg-pull-upEXKXpcfg-pull-downE[K[pcfg-pull-noneEWKWpcfg-pull-none-12ma EZKZsleepglobal-pwroffWEVKVddrio-pwroffWddr0-retentionXddr1-retentionXi2c0i2c0-xfer WWE;K;i2c1i2c1-xfer WWE#K#i2c2i2c2-xfer  W WEBKBi2c3i2c3-xfer WWE$K$i2c4i2c4-xfer WWE%K%i2c5i2c5-xfer WWE&K&i2s0i2s0-bus`WWWWWWEIKIsdmmcsdmmc-clkWsdmmc-cmdXsdmmc-cdXsdmmc-bus1Xsdmmc-bus4@XXXXsdio0sdio0-bus1Xsdio0-bus4@YYYYEKsdio0-cmdYEKsdio0-clkYE K sdio0-cdXsdio0-wpXsdio0-pwrXsdio0-bkpwrXsdio0-intXwifienable-hWEcKcbt-enable-lWEbKbsdio1sdio1-bus1Xsdio1-bus4@XXXXsdio1-cdXsdio1-wpXsdio1-bkpwrXsdio1-intXsdio1-cmdXsdio1-clkWsdio1-pwr Xemmcemmc-clkYEKemmc-cmdYEKemmc-pwr Xemmc-bus1Xemmc-bus4@XXXXemmc-bus8YYYYYYYYEKemmc-reset WE^K^spi0spi0-clk XEKspi0-cs0 XEKspi0-txXEKspi0-rxXEKspi0-cs1Xspi1spi1-clk XEKspi1-cs0 XEKspi1-rxXEKspi1-txXEKspi2spi2-cs1Xspi2-clkXEKspi2-cs0XE"K"spi2-rxXE!K!spi2-tx XE K uart0uart0-xfer XWE'K'uart0-ctsXE(K(uart0-rtsWE)K)uart1uart1-xfer X WE*K*uart1-cts Xuart1-rts Wuart2uart2-xfer XWE+K+uart3uart3-xfer XWE,K,uart3-cts Xuart3-rts Wuart4uart4-xfer  X WE-K-uart4-ctsXuart4-rtsWtsadcotp-gpio WE5K5otp-out WE6K6pwm0pwm0-pinWECKCpwm1pwm1-pinWEDKDpwm2pwm2-pinWEEKEpwm3pwm3-pinWEFKFgmacrgmii-pinsWWWWZZZZWWW ZZWWrmii-pinsWWWWWWWWWWspdifspdif-tx WEHKHpcfg-pull-none-drv-8maEYKYpcfg-pull-up-drv-8mapcfg-output-high pcfg-output-lowbuttonspwr-key-lXE\K\pmicpmic-int-lXE=K=dvs-1 [E>K>dvs-2[E?K?rebootap-warm-reset-h WE]K]recovery-switchrec-mode-l Xtpmtpm-int-hWwrite-protectfw-wp-apWgpio-keys gpio-keysvdefault\power"Power <(t3dhgpio-restart gpio-restart < vdefault]Eemmc-pwrseqmmc-pwrseq-emmc^vdefault N_ EKio-domains"rockchip,rk3288-io-voltage-domain7Z@do}@@`sdio-pwrseqmmc-pwrseq-simple2a ext_clockvdefaultbc NdE K vcc-5vregulator-fixedvcc_5vLK@/LK@EeKevcc33-sysregulator-fixed vcc33_sys2Z/2ZEKvcc50-hdmiregulator-fixed vcc50_hdmie A vdefaultfvcc33_ioregulator-fixed vcc33_ioE@K@ #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2device_typereginterruptsinterrupt-affinityenable-methodrockchip,pmuresetsoperating-points#cooling-cellsclock-latencyclockscpu0-supplylinux,phandleranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredportsclock-freq-min-maxfifo-depthbroken-cdbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablenum-slotspinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplycap-mmc-highspeedrockchip,default-sample-phasedisable-wp#io-channel-cellsdmasdma-namesrx-sample-delay-nsi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedreg-shiftreg-io-widthassigned-clocksassigned-clock-ratespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfphysphy-namesneeds-reset-on-resumedr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmaassigned-clock-parentsrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc7-supplyvcc8-supplyvddio-supplydvs-gpiosvcc11-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltregulator-suspend-mem-disabled#pwm-cells#power-domain-cells#reset-cells#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channelspower-domainsiommusremote-endpoint#iommu-cellsddc-i2c-businterrupt-controller#interrupt-cells#phy-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowlabellinux,codedebounce-intervalpriorityreset-gpiosbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyvin-supplyenable-active-highgpio