'e8#(#$rockchip,rk3228-evbrockchip,rk3228&!7Rockchip RK3228 Evaluation boardchosenaliases=/serial@11010000E/serial@11020000M/serial@11030000memoryUmemorya`@cpuscpu@f00Ucpuarm,cortex-a7ael sB@}@cpu@f01Ucpuarm,cortex-a7aecpu@f02Ucpuarm,cortex-a7aecpu@f03Ucpuarm,cortex-a7aeamba simple-buspdma@110f0000arm,pl330arm,primecella@ apb_pclkarm-pmuarm,cortex-a7-pmu0LMNOtimerarm,armv7-timer0   n6oscillator fixed-clockn6xin24m2syscon@11000000sysconaserial@11010000snps,dw-apb-uarta 7n6MUbaudclkapb_pclk?default M Wa ndisabledserial@11020000snps,dw-apb-uarta 8n6NVbaudclkapb_pclk?defaultM Wa ndisabledserial@11030000snps,dw-apb-uarta 9n6OWbaudclkapb_pclk?defaultM Wanokayi2c@11050000rockchip,rk3228-i2ca $i2cL?defaultM  ndisabledi2c@11060000rockchip,rk3228-i2ca %i2cM?defaultM  ndisabledi2c@11070000rockchip,rk3228-i2ca &i2cN?defaultM ndisabledi2c@11080000rockchip,rk3228-i2ca 'i2cO?defaultM ndisabledpwm@110b0000rockchip,rk3288-pwma u^pwm?defaultM ndisabledpwm@110b0010rockchip,rk3288-pwma u^pwm?defaultM ndisabledpwm@110b0020rockchip,rk3288-pwma u^pwm?defaultM ndisabledpwm@110b0030rockchip,rk3288-pwma 0u^pwm?defaultM ndisabledtimer@110c0000rockchip,rk3288-timera  + a timerpclkclock-controller@110e0000rockchip,rk3228-crua2#gthermal-zonescpu-thermaldtripscpu_alert0p\passivecpu_alert1$\passivecpu_crit_ \criticalcooling-mapsmap0  map1  tsadc@11150000rockchip,rk3228-tsadca :HXtsadcapb_pclkeW tsadc-apb?initdefaultsleepM*4>Tsnokaykdwmmc@30020000rockchip,rk3288-dw-mshca0@ <4`<4` Guybiuciuciu_drvciu_sample?default Mnokayinterrupt-controller@32010000 arm,gic-4001 a22 2@ 2`   pinctrlrockchip,rk3228-pinctrlgpio0@11110000rockchip,gpio-banka 3@BR1gpio1@11120000rockchip,gpio-banka 4ABR1gpio2@11130000rockchip,gpio-banka 5BBR1gpio3@11140000rockchip,gpio-banka 6CBR1pcfg-pull-up^pcfg-pull-downkpcfg-pull-nonezemmcemmc-clkemmc-cmdemmc-bus8i2c0i2c0-xfer   i2c1i2c1-xfer   i2c2i2c2-xfer i2c3i2c3-xfer pwm0pwm0-pinpwm1pwm1-pinpwm2pwm2-pin pwm3pwm3-pin tsadcotp-gpiootp-outuart0uart0-xfer uart0-ctsuart0-rts  uart1uart1-xfer     uart1-ctsuart1-rts uart2uart2-xfer   uart2-ctsuart2-rts #address-cells#size-cellscompatibleinterrupt-parentmodelserial0serial1serial2device_typeregresetsoperating-points#cooling-cellsclock-latencyclockslinux,phandlerangesinterrupts#dma-cellsclock-namesinterrupt-affinityarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellspinctrl-namespinctrl-0reg-shiftreg-io-widthstatus#pwm-cellsrockchip,grf#reset-cellsassigned-clocksassigned-clock-ratespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityclock-freq-min-maxbus-widthdefault-sample-phasenum-slotsfifo-depthcap-mmc-highspeedmmc-ddr-1_8vdisable-wpnon-removableinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disablerockchip,pins