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C?L[bch8k},,",( 6/@>ROR`w(+@partition@0SPLpartition@1U-bootpartition@2 U-Boot Env&partition@3Kernel(Ppartition@4 File Systemxsham@53100000ti,omap4-shamshamSm ($rxaes@53500000 ti,omap4-aesaesSPg((txrxmcasp@48038000ti,am33xx-mcasp-audiomcasp0H F@.mpudatPQtxrx disabled(( txrxmcasp@4803C000ti,am33xx-mcasp-audiomcasp1H F@@.mpudatRStxrx disabled( ( txrxrng@48310000 ti,omap4-rngrngH1 omemory@80000000memoryledsdefaultA gpio-ledsled0com:green:user FBonfixedregulator0regulator-fixedvbatLK@LK@G.M.fixedregulator1regulator-fixedvmmc2Z2ZG0M0hdmiti,tilcdc,slaveC defaultoffDEokayleds_basedefaultF gpio-ledsled0base:red:user FBoffled1base:green:user FGoff compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2serial3serial4serial5d_can0d_can1usb0usb1phy0phy1ethernet0ethernet1device_typeregoperating-pointsvoltage-toleranceclocksclock-namesclock-latencycpu0-supplyinterruptsti,hwmodsrangesreg-namesti,pm-firmwarelinux,phandle#clock-cellsclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-rate-parentti,bit-shiftti,index-power-of-twopinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinsti,rprocmboxes#dma-cellsdma-requestsdma-mastersinterrupt-controller#interrupt-cellsinterrupt-namesti,tptcsti,edma-memcpy-channelsgpio-controller#gpio-cellsstatusdmasdma-namespinctrl-namespinctrl-0vcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-compatibleregulator-always-onregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onti,dual-voltti,needs-special-resetti,needs-special-hs-handlingvmmc-supplybus-width#hwlock-cellssyscon-raminit#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-send-noirqti,mbox-txti,mbox-rxti,timer-alwonti,timer-pwmti,spi-num-csti,ctrl_moddr_modementor,multipointmentor,num-epsmentor,ram-bitsmentor,powerphys#dma-channels#dma-requests#pwm-cellscpdma_channelsale_entriesbd_ram_sizeno_bd_rammac_controlslavesactive_slavecpts_clock_multcpts_clock_shiftsysconbus_freqmac-addressphy_idphy-modermii-clock-ext#io-channel-cellsti,no-idle-on-initgpmc,num-csgpmc,num-waitpinsrb-gpiosnand-bus-widthti,nand-ecc-optgpmc,device-widthgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,clk-activation-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nsti,elm-idlabeldefault-statei2cpinctrl-1