88(  timll,omap3-devkit8000ti,omap3 +,7TimLL OMAP3 Devkit8000 with 7.0'' LCD panelaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000 d/display m/connector0 v/connector1cpus+cpu@0arm,cortex-a8cpucpu(HАg8 Odp` 'ppmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus + pinmux@30 ti,omap3-padconfpinctrl-single08+!pinmux_twl4030_pins>ARXpinmux_dss_dpi_pins>RXscm_conf@270sysconsimple-busp0+ p0RXpbias_regulator@2b0ti,pbias-omap3ti,pbias-omap`pbias_mmc_omap2430gpbias_mmc_omap2430vw@-RXclocks+mcbsp5_mux_fck@68ti,composite-mux-clockhRXmcbsp5_fckti,composite-clockRXmcbsp1_mux_fck@4ti,composite-mux-clockR X mcbsp1_fckti,composite-clock RXmcbsp2_mux_fck@4ti,composite-mux-clock R X mcbsp2_fckti,composite-clock RXmcbsp3_mux_fck@68ti,composite-mux-clock hRXmcbsp3_fckti,composite-clock RXmcbsp4_mux_fck@68ti,composite-mux-clock hRXmcbsp4_fckti,composite-clockRXclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+!pinmux_twl4030_vpins >RXaes@480c5000 ti,omap3-aesaesH PPABtxrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clockYRXosc_sys_ck@d40 ti,mux-clock @RXsys_ck@1270ti,divider-clockpRXsys_clkout1@d70ti,gate-clock pdpll3_x2_ckfixed-factor-clock dpll3_m2x2_ckfixed-factor-clock RXdpll4_x2_ckfixed-factor-clock corex2_fckfixed-factor-clock RXwkup_l4_ickfixed-factor-clock RMXMcorex2_d3_fckfixed-factor-clock RXcorex2_d5_fckfixed-factor-clock RXclockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockR?X?virt_12m_ck fixed-clockRXvirt_13m_ck fixed-clock]@RXvirt_19200000_ck fixed-clock$RXvirt_26000000_ck fixed-clockRXvirt_38_4m_ck fixed-clockIRXdpll4_ck@d00ti,omap3-dpll-per-clock D 0RXdpll4_m2_ck@d48ti,divider-clock? HRXdpll4_m2x2_mul_ckfixed-factor-clock R X dpll4_m2x2_ck@d00ti,gate-clock  R!X!omap_96m_alwon_fckfixed-factor-clock! R(X(dpll3_ck@d00ti,omap3-dpll-core-clock @ 0RXdpll3_m3_ck@1140ti,divider-clock@R"X"dpll3_m3x2_mul_ckfixed-factor-clock" R#X#dpll3_m3x2_ck@d00ti,gate-clock#  R$X$emu_core_alwon_ckfixed-factor-clock$ RaXasys_altclk fixed-clockR-X-mcbsp_clks fixed-clockRXdpll3_m2_ck@d40ti,divider-clock @RXcore_ckfixed-factor-clock R%X%dpll1_fck@940ti,divider-clock% @R&X&dpll1_ck@904ti,omap3-dpll-clock&  $ @ 4RXdpll1_x2_ckfixed-factor-clock R'X'dpll1_x2m2_ck@944ti,divider-clock' DR;X;cm_96m_fckfixed-factor-clock( R)X)omap_96m_fck@d40 ti,mux-clock) @RDXDdpll4_m3_ck@e40ti,divider-clock @R*X*dpll4_m3x2_mul_ckfixed-factor-clock* R+X+dpll4_m3x2_ck@d00ti,gate-clock+ R,X,omap_54m_fck@d40 ti,mux-clock,- @R7X7cm_96m_d2_fckfixed-factor-clock) R.X.omap_48m_fck@d40 ti,mux-clock.- @R/X/omap_12m_fckfixed-factor-clock/ RFXFdpll4_m4_ck@e40ti,divider-clock @R0X0dpll4_m4x2_mul_ckti,fixed-factor-clock0,:GR1X1dpll4_m4x2_ck@d00ti,gate-clock1 GRXdpll4_m5_ck@f40ti,divider-clock?@R2X2dpll4_m5x2_mul_ckti,fixed-factor-clock2,:GR3X3dpll4_m5x2_ck@d00ti,gate-clock3 GRiXidpll4_m6_ck@1140ti,divider-clock?@R4X4dpll4_m6x2_mul_ckfixed-factor-clock4 R5X5dpll4_m6x2_ck@d00ti,gate-clock5 R6X6emu_per_alwon_ckfixed-factor-clock6 RbXbclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock% pR8X8clkout2_src_mux_ck@d70ti,composite-mux-clock%)7 pR9X9clkout2_src_ckti,composite-clock89R:X:sys_clkout2@d70ti,divider-clock:@ pZmpu_ckfixed-factor-clock; R<X<arm_fck@924ti,divider-clock< $emu_mpu_alwon_ckfixed-factor-clock< RcXcl3_ick@a40ti,divider-clock% @R=X=l4_ick@a40ti,divider-clock= @R>X>rm_ick@c40ti,divider-clock> @gpt10_gate_fck@a00ti,composite-gate-clock  R@X@gpt10_mux_fck@a40ti,composite-mux-clock? @RAXAgpt10_fckti,composite-clock@Agpt11_gate_fck@a00ti,composite-gate-clock  RBXBgpt11_mux_fck@a40ti,composite-mux-clock? @RCXCgpt11_fckti,composite-clockBCcore_96m_fckfixed-factor-clockD RXmmchs2_fck@a00ti,wait-gate-clock RXmmchs1_fck@a00ti,wait-gate-clock RXi2c3_fck@a00ti,wait-gate-clock RXi2c2_fck@a00ti,wait-gate-clock RXi2c1_fck@a00ti,wait-gate-clock RXmcbsp5_gate_fck@a00ti,composite-gate-clock  RXmcbsp1_gate_fck@a00ti,composite-gate-clock  RXcore_48m_fckfixed-factor-clock/ REXEmcspi4_fck@a00ti,wait-gate-clockE RXmcspi3_fck@a00ti,wait-gate-clockE RXmcspi2_fck@a00ti,wait-gate-clockE RXmcspi1_fck@a00ti,wait-gate-clockE RXuart2_fck@a00ti,wait-gate-clockE RXuart1_fck@a00ti,wait-gate-clockE  RXcore_12m_fckfixed-factor-clockF RGXGhdq_fck@a00ti,wait-gate-clockG RXcore_l3_ickfixed-factor-clock= RHXHsdrc_ick@a10ti,wait-gate-clockH RXgpmc_fckfixed-factor-clockH core_l4_ickfixed-factor-clock> RIXImmchs2_ick@a10ti,omap3-interface-clockI RXmmchs1_ick@a10ti,omap3-interface-clockI RXhdq_ick@a10ti,omap3-interface-clockI RXmcspi4_ick@a10ti,omap3-interface-clockI RXmcspi3_ick@a10ti,omap3-interface-clockI RXmcspi2_ick@a10ti,omap3-interface-clockI RXmcspi1_ick@a10ti,omap3-interface-clockI RXi2c3_ick@a10ti,omap3-interface-clockI RXi2c2_ick@a10ti,omap3-interface-clockI RXi2c1_ick@a10ti,omap3-interface-clockI RXuart2_ick@a10ti,omap3-interface-clockI RXuart1_ick@a10ti,omap3-interface-clockI  RXgpt11_ick@a10ti,omap3-interface-clockI  RXgpt10_ick@a10ti,omap3-interface-clockI  RXmcbsp5_ick@a10ti,omap3-interface-clockI  RXmcbsp1_ick@a10ti,omap3-interface-clockI  RXomapctrl_ick@a10ti,omap3-interface-clockI RXdss_tv_fck@e00ti,gate-clock7RXdss_96m_fck@e00ti,gate-clockDRXdss2_alwon_fck@e00ti,gate-clockRXdummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock RJXJgpt1_mux_fck@c40ti,composite-mux-clock? @RKXKgpt1_fckti,composite-clockJKaes2_ick@a10ti,omap3-interface-clockI RXwkup_32k_fckfixed-factor-clock? RLXLgpio1_dbck@c00ti,gate-clockL RXsha12_ick@a10ti,omap3-interface-clockI RXwdt2_fck@c00ti,wait-gate-clockL RXwdt2_ick@c10ti,omap3-interface-clockM RXwdt1_ick@c10ti,omap3-interface-clockM RXgpio1_ick@c10ti,omap3-interface-clockM RXomap_32ksync_ick@c10ti,omap3-interface-clockM RXgpt12_ick@c10ti,omap3-interface-clockM RXgpt1_ick@c10ti,omap3-interface-clockM RXper_96m_fckfixed-factor-clock( R X per_48m_fckfixed-factor-clock/ RNXNuart3_fck@1000ti,wait-gate-clockN RXgpt2_gate_fck@1000ti,composite-gate-clockROXOgpt2_mux_fck@1040ti,composite-mux-clock?@RPXPgpt2_fckti,composite-clockOPgpt3_gate_fck@1000ti,composite-gate-clockRQXQgpt3_mux_fck@1040ti,composite-mux-clock?@RRXRgpt3_fckti,composite-clockQRgpt4_gate_fck@1000ti,composite-gate-clockRSXSgpt4_mux_fck@1040ti,composite-mux-clock?@RTXTgpt4_fckti,composite-clockSTgpt5_gate_fck@1000ti,composite-gate-clockRUXUgpt5_mux_fck@1040ti,composite-mux-clock?@RVXVgpt5_fckti,composite-clockUVgpt6_gate_fck@1000ti,composite-gate-clockRWXWgpt6_mux_fck@1040ti,composite-mux-clock?@RXXXgpt6_fckti,composite-clockWXgpt7_gate_fck@1000ti,composite-gate-clockRYXYgpt7_mux_fck@1040ti,composite-mux-clock?@RZXZgpt7_fckti,composite-clockYZgpt8_gate_fck@1000ti,composite-gate-clock R[X[gpt8_mux_fck@1040ti,composite-mux-clock?@R\X\gpt8_fckti,composite-clock[\gpt9_gate_fck@1000ti,composite-gate-clock R]X]gpt9_mux_fck@1040ti,composite-mux-clock?@R^X^gpt9_fckti,composite-clock]^per_32k_alwon_fckfixed-factor-clock? R_X_gpio6_dbck@1000ti,gate-clock_RXgpio5_dbck@1000ti,gate-clock_RXgpio4_dbck@1000ti,gate-clock_RXgpio3_dbck@1000ti,gate-clock_RXgpio2_dbck@1000ti,gate-clock_ RXwdt3_fck@1000ti,wait-gate-clock_ RXper_l4_ickfixed-factor-clock> R`X`gpio6_ick@1010ti,omap3-interface-clock`RXgpio5_ick@1010ti,omap3-interface-clock`RXgpio4_ick@1010ti,omap3-interface-clock`RXgpio3_ick@1010ti,omap3-interface-clock`RXgpio2_ick@1010ti,omap3-interface-clock` RXwdt3_ick@1010ti,omap3-interface-clock` RXuart3_ick@1010ti,omap3-interface-clock` RXuart4_ick@1010ti,omap3-interface-clock`RXgpt9_ick@1010ti,omap3-interface-clock` RXgpt8_ick@1010ti,omap3-interface-clock` RXgpt7_ick@1010ti,omap3-interface-clock`RXgpt6_ick@1010ti,omap3-interface-clock`RXgpt5_ick@1010ti,omap3-interface-clock`RXgpt4_ick@1010ti,omap3-interface-clock`RXgpt3_ick@1010ti,omap3-interface-clock`RXgpt2_ick@1010ti,omap3-interface-clock`RXmcbsp2_ick@1010ti,omap3-interface-clock`RXmcbsp3_ick@1010ti,omap3-interface-clock`RXmcbsp4_ick@1010ti,omap3-interface-clock`RXmcbsp2_gate_fck@1000ti,composite-gate-clockR X mcbsp3_gate_fck@1000ti,composite-gate-clockR X mcbsp4_gate_fck@1000ti,composite-gate-clockRXemu_src_mux_ck@1140 ti,mux-clockabc@RdXdemu_src_ckti,clkdm-gate-clockdReXepclk_fck@1140ti,divider-clocke@pclkx2_fck@1140ti,divider-clocke@atclk_fck@1140ti,divider-clocke@traceclk_src_fck@1140 ti,mux-clockabc@RfXftraceclk_fck@1140ti,divider-clockf @secure_32k_fck fixed-clockRgXggpt12_fckfixed-factor-clockg wdt1_fckfixed-factor-clockg security_l4_ick2fixed-factor-clock> RhXhaes1_ick@a14ti,omap3-interface-clockh rng_ick@a14ti,omap3-interface-clockh sha11_ick@a14ti,omap3-interface-clockh des1_ick@a14ti,omap3-interface-clockh cam_mclk@f00ti,gate-clockiGcam_ick@f10!ti,omap3-no-wait-interface-clock>RXcsi2_96m_fck@f00ti,gate-clockRXsecurity_l3_ickfixed-factor-clock= RjXjpka_ick@a14ti,omap3-interface-clockj icr_ick@a10ti,omap3-interface-clockI des2_ick@a10ti,omap3-interface-clockI mspro_ick@a10ti,omap3-interface-clockI mailboxes_ick@a10ti,omap3-interface-clockI ssi_l4_ickfixed-factor-clock> RqXqsr1_fck@c00ti,wait-gate-clock sr2_fck@c00ti,wait-gate-clock sr_l4_ickfixed-factor-clock> dpll2_fck@40ti,divider-clock%@RkXkdpll2_ck@4ti,omap3-dpll-clockk$@4pRlXldpll2_m2_ck@44ti,divider-clocklDRmXmiva2_ck@0ti,wait-gate-clockmRXmodem_fck@a00ti,omap3-interface-clock RXsad2d_ick@a10ti,omap3-interface-clock= RXmad2d_ick@a18ti,omap3-interface-clock= RXmspro_fck@a00ti,wait-gate-clock ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock RnXnssi_ssr_div_fck_3430es2@a40ti,composite-divider-clock @$RoXossi_ssr_fck_3430es2ti,composite-clocknoRpXpssi_sst_fck_3430es2fixed-factor-clockp RXhsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clockH RXssi_ick_3430es2@a10ti,omap3-ssi-interface-clockq RXusim_gate_fck@c00ti,composite-gate-clockD  R|X|sys_d2_ckfixed-factor-clock RsXsomap_96m_d2_fckfixed-factor-clockD RtXtomap_96m_d4_fckfixed-factor-clockD RuXuomap_96m_d8_fckfixed-factor-clockD RvXvomap_96m_d10_fckfixed-factor-clockD RwXwdpll5_m2_d4_ckfixed-factor-clockr RxXxdpll5_m2_d8_ckfixed-factor-clockr RyXydpll5_m2_d16_ckfixed-factor-clockr RzXzdpll5_m2_d20_ckfixed-factor-clockr R{X{usim_mux_fck@c40ti,composite-mux-clock(stuvwxyz{ @R}X}usim_fckti,composite-clock|}usim_ick@c10ti,omap3-interface-clockM  RXdpll5_ck@d04ti,omap3-dpll-clock  $ L 4pR~X~dpll5_m2_ck@d50ti,divider-clock~ PRrXrsgx_gate_fck@b00ti,composite-gate-clock% RXcore_d3_ckfixed-factor-clock% RXcore_d4_ckfixed-factor-clock% RXcore_d6_ckfixed-factor-clock% RXomap_192m_alwon_fckfixed-factor-clock! RXcore_d2_ckfixed-factor-clock% RXsgx_mux_fck@b40ti,composite-mux-clock ) @RXsgx_fckti,composite-clocksgx_ick@b10ti,wait-gate-clock= RXcpefuse_fck@a08ti,gate-clock RXts_fck@a08ti,gate-clock? RXusbtll_fck@a08ti,wait-gate-clockr RXusbtll_ick@a18ti,omap3-interface-clockI RXmmchs3_ick@a10ti,omap3-interface-clockI RXmmchs3_fck@a00ti,wait-gate-clock RXdss1_alwon_fck_3430es2@e00ti,dss-gate-clockGRXdss_ick_3430es2@e10ti,omap3-dss-interface-clock>RXusbhost_120m_fck@1400ti,gate-clockrRXusbhost_48m_fck@1400ti,dss-gate-clock/RXusbhost_ick@1410ti,omap3-dss-interface-clock>RXclockdomainscore_l3_clkdmti,clockdomaindpll3_clkdmti,clockdomaindpll1_clkdmti,clockdomainper_clkdmti,clockdomainhemu_clkdmti,clockdomainedpll4_clkdmti,clockdomainwkup_clkdmti,clockdomain$dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaincam_clkdmti,clockdomainiva2_clkdmti,clockdomaindpll2_clkdmti,clockdomainld2d_clkdmti,clockdomain dpll5_clkdmti,clockdomain~sgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain counter@48320000ti,omap-counter32kH2  counter_32kinterrupt-controller@48200000ti,omap3-intcH RXdma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaH`  `RXgpio@48310000ti,omap3-gpioH1gpio1RXgpio@49050000ti,omap3-gpioIgpio2gpio@49052000ti,omap3-gpioI gpio3gpio@49054000ti,omap3-gpioI@ gpio4gpio@49056000ti,omap3-gpioI`!gpio5gpio@49058000ti,omap3-gpioI"gpio6RXserial@4806a000ti,omap3-uartH H12txrxuart1lserial@4806c000ti,omap3-uartHI34txrxuart2lserial@49020000ti,omap3-uartIJ56txrxuart3li2c@48070000 ti,omap3-i2cH8txrx+i2c1'@twl@48H ti,twl4030defaultaudioti,twl4030-audiocodecrtcti,twl4030-rtc bciti,twl4030-bci )watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1v ' regulator-vdacti,twl4030-vdacvw@w@RXregulator-vioti,twl4030-viovw@w@RXregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1v:0RXregulator-vmmc2ti,twl4030-vmmc2v:0regulator-vusb1v5ti,twl4030-vusb1v5RXregulator-vusb1v8ti,twl4030-vusb1v8RXregulator-vusb3v1ti,twl4030-vusb3v1RXregulator-vpll1ti,twl4030-vpll1 gvdds_dsivw@w@RXregulator-vpll2ti,twl4030-vpll2vw@w@regulator-vsimti,twl4030-vsimvw@-RXgpioti,twl4030-gpio7CRXtwl4030-usbti,twl4030-usb P^lzpwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadD?  @A Bsrmadcti,twl4030-madci2c@48072000 ti,omap3-i2cH 9txrx+i2c2RXi2c@48060000 ti,omap3-i2cH=txrx+i2c3 disabledmailbox@48094000ti,omap3-mailboxmailboxH @dsp  spi@48098000ti,omap2-mcspiH A+mcspi1(@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspiH B+mcspi2( +,-.tx0rx0tx1rx1ads7846@0 ti,ads78466A`  S`ir{ spi@480b8000ti,omap2-mcspiH [+mcspi3( tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiH 0+mcspi4(FGtx0rx01w@480b2000 ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-hsmmcH Smmc1=>txrx!-=mmc@480b4000ti,omap3-hsmmcH @Vmmc2/0txrx disabledmmc@480ad000ti,omap3-hsmmcH ^mmc3MNtxrx disabledmmu@480bd400Gti,omap2-iommuH mmu_ispTRXmmu@5d000000Gti,omap2-iommu]mmu_iva disabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2 disabledmcbsp@48074000ti,omap3-mcbspH@dmpu ;< ncommontxrx~mcbsp1 txrxfck disabledmcbsp@49022000ti,omap3-mcbspI I dmpusidetone>?ncommontxrxsidetone~mcbsp2mcbsp2_sidetone!"txrxfckickokayRXmcbsp@49024000ti,omap3-mcbspI@I dmpusidetoneYZncommontxrxsidetone~mcbsp3mcbsp3_sidetonetxrxfckick disabledmcbsp@49026000ti,omap3-mcbspI`dmpu 67 ncommontxrx~mcbsp4txrxfck disabledmcbsp@48096000ti,omap3-mcbspH `dmpu QR ncommontxrx~mcbsp5txrxfck disabledsham@480c3000ti,omap3-shamshamH 0d1Erxsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_coreH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivaH timer@48318000ti,omap3430-timerH1%timer1timer@49032000ti,omap3430-timerI &timer2timer@49034000ti,omap3430-timerI@'timer3timer@49036000ti,omap3430-timerI`(timer4timer@49038000ti,omap3430-timerI)timer5timer@4903a000ti,omap3430-timerI*timer6timer@4903c000ti,omap3430-timerI+timer7timer@4903e000ti,omap3430-timerI,timer8timer@49040000ti,omap3430-timerI-timer9timer@48086000ti,omap3430-timerH`.timer10timer@48088000ti,omap3430-timerH/timer11timer@48304000ti,omap3430-timerH0@_timer12usbhstll@48062000 ti,usbhs-tllH N usb_tll_hsusbhshost@48064000ti,usbhs-hostH@ usb_host_hs+ohci@48064400ti,ohci-omap3HD Lehci@48064800 ti,ehci-omapHH Mgpmc@6e000000ti,omap3430-gpmcgpmcnrxtx+,RXnand@0,0ti,omap2-nand  sw&4,F,Xg"z,(6@RR(+x-loader@0 X-Loaderbootloaders@80000U-Bootbootloaders_env@260000 U-Boot Env&kernel@280000Kernel(@filesystem@680000 File Systemhethernet@0,0davicom,dm9000  );Ic&4FXgz0}66ZZusb_otg_hs@480ab000ti,omap3-musbH \]nmcdma usb_otg_hs& dss@48050000 ti,omap3-dssHok dss_corefck+default/?dispc@48050400ti,omap3-dispcH dss_dispcfckencoder@4804fc00 ti,omap3-dsiHH@H dprotophypll disabled dss_dsi1 fcksys_clkencoder@48050800ti,omap3-rfbiH disabled dss_rfbifckickencoder@48050c00ti,omap3-vencH ok dss_vencfckOportendpoint[kRXportendpoint[wRXssi-controller@48058000 ti,omap3-ssissiokHHdsysgddGngdd_mpu+ p ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portHHdtxrx CDssi-port@4805b000ti,omap3-ssi-portHHdtxrx EFpinmux@480025d8 ti,omap3-padconfpinctrl-singleH%$+!isp@480bc000 ti,omap3-ispH H |`lports+bandgap@48002524H%$ti,omap34xx-bandgapmemory@80000000memoryleds gpio-ledsheartbeatdevkit8000::led1 on heartbeatmmcdevkit8000::led2 onnoneusrdevkit8000::led3 onusrpmu_statdevkit8000::pmu_stat soundti,omap-twl4030 devkit8000IExt SpkPREDRIVELExt SpkPREDRIVERMAINMICMain MicMain MicMic Bias 1gpio_keys gpio-keysuseruser encoder0 ti,tfp410 ports+port@0endpoint[port@1endpoint[RXconnector0dvi-connectordvi  portendpoint[RXconnector1svideo-connectortvportendpoint[RXdisplay panel-dpilcd 'portendpoint[RXpanel-timingbZ 4  < D Q ]0 g s       compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2display0display1display2device_typeregclocksclock-namesclock-latencyoperating-pointsinterruptsti,hwmodsranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinslinux,phandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyti,use-ledsti,pulldownsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cellsstatus#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csvcc-supplyspi-max-frequencypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,debounce-maxti,debounce-tolti,debounce-repti,keep-vref-onti,settle-delay-usecwakeup-sourceti,dual-voltpbias-supplyvmmc-supplyvmmc_aux-supplybus-width#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-securegpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthdavicom,no-eepromgpmc,mux-add-datagpmc,wait-pingpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,oe-on-nsgpmc,we-on-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsmultipointnum-epsram-bitsvdds_dsi-supplyvdda_dac-supplyvdda-supplyremote-endpointti,channelsdata-linesiommusti,phy-type#thermal-sensor-cellsgpiosdefault-statelinux,default-triggerti,modelti,mcbspti,audio-routinglinux,codepowerdown-gpiosdigitalddc-i2c-busenable-gpioshactivevactivehfront-porchhback-porchhsync-lenvback-porchvfront-porchvsync-lenhsync-activevsync-activede-activepixelclk-active