8()isee,omap3-igep0020ti,omap36xxti,omap3 +!7IGEPv2 Rev. C (TI OMAP AM/DM37x)aliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000d/ocp@68000000/serial@49042000cpus+cpu@0arm,cortex-a8lcpux|cpus 'O 57pmu@54000000arm,cortex-a8-pmuxTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busxh +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busx + pinmux@30 ti,omap3-padconfpinctrl-singlex08++default9pinmux_uart1_pinsCRLW]pinmux_uart3_pinsCnpW]pinmux_mcbsp2_pins C W]pinmux_mmc1_pins0CW]pinmux_mmc2_pins0C(*,.02W]pinmux_i2c1_pinsCW]pinmux_i2c3_pinsCW]pinmux_twl4030_pinsCAW]pinmux_tfp410_pinsCW]pinmux_dss_dpi_pinsCW]pinmux_uart2_pins CDFHJW]pinmux_smsc9221_pinsCW]pinmux_lbee1usjyc_pinsC68:W]scm_conf@270sysconsimple-busxp0+ p0W]pbias_regulator@2b0ti,pbias-omap3ti,pbias-omapxepbias_mmc_omap2430lpbias_mmc_omap2430{w@-W]clocks+mcbsp5_mux_fck@68ti,composite-mux-clock|xhW ] mcbsp5_fckti,composite-clock| W]mcbsp1_mux_fck@4ti,composite-mux-clock|xW ] mcbsp1_fckti,composite-clock| W]mcbsp2_mux_fck@4ti,composite-mux-clock| xW]mcbsp2_fckti,composite-clock| W]mcbsp3_mux_fck@68ti,composite-mux-clock| xhW]mcbsp3_fckti,composite-clock|W]mcbsp4_mux_fck@68ti,composite-mux-clock| xhW]mcbsp4_fckti,composite-clock|W]clockdomainspinmux@a00 ti,omap3-padconfpinctrl-singlex \+pinmux_twl4030_vpins CW]aes@480c5000 ti,omap3-aesaesxH PPABtxrxprm@48306000 ti,omap3-prmxH0`@ clocks+virt_16_8m_ck fixed-clockYW]osc_sys_ck@d40 ti,mux-clock|x @W]sys_ck@1270ti,divider-clock|xpW]sys_clkout1@d70ti,gate-clock|x pdpll3_x2_ckfixed-factor-clock|dpll3_m2x2_ckfixed-factor-clock|W]dpll4_x2_ckfixed-factor-clock|corex2_fckfixed-factor-clock|W ] wkup_l4_ickfixed-factor-clock|WO]Ocorex2_d3_fckfixed-factor-clock| W]corex2_d5_fckfixed-factor-clock| W]clockdomainscm@48004000 ti,omap3-cmxH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockWA]Avirt_12m_ck fixed-clockW]virt_13m_ck fixed-clock]@W]virt_19200000_ck fixed-clock$W]virt_26000000_ck fixed-clockW]virt_38_4m_ck fixed-clockIW]dpll4_ck@d00ti,omap3-dpll-per-j-type-clock|x D 0W]dpll4_m2_ck@d48ti,divider-clock|?x HW!]!dpll4_m2x2_mul_ckfixed-factor-clock|!W"]"dpll4_m2x2_ck@d00ti,hsdiv-gate-clock|"x W#]#omap_96m_alwon_fckfixed-factor-clock|#W*]*dpll3_ck@d00ti,omap3-dpll-core-clock|x @ 0W]dpll3_m3_ck@1140ti,divider-clock|x@W$]$dpll3_m3x2_mul_ckfixed-factor-clock|$W%]%dpll3_m3x2_ck@d00ti,hsdiv-gate-clock|% x W&]&emu_core_alwon_ckfixed-factor-clock|&Wc]csys_altclk fixed-clockW/]/mcbsp_clks fixed-clockW]dpll3_m2_ck@d40ti,divider-clock|x @W]core_ckfixed-factor-clock|W']'dpll1_fck@940ti,divider-clock|'x @W(](dpll1_ck@904ti,omap3-dpll-clock|(x  $ @ 4W]dpll1_x2_ckfixed-factor-clock|W)])dpll1_x2m2_ck@944ti,divider-clock|)x DW=]=cm_96m_fckfixed-factor-clock|*W+]+omap_96m_fck@d40 ti,mux-clock|+x @WF]Fdpll4_m3_ck@e40ti,divider-clock| x@W,],dpll4_m3x2_mul_ckfixed-factor-clock|,W-]-dpll4_m3x2_ck@d00ti,hsdiv-gate-clock|-x W.].omap_54m_fck@d40 ti,mux-clock|./x @W9]9cm_96m_d2_fckfixed-factor-clock|+W0]0omap_48m_fck@d40 ti,mux-clock|0/x @W1]1omap_12m_fckfixed-factor-clock|1WH]Hdpll4_m4_ck@e40ti,divider-clock| x@W2]2dpll4_m4x2_mul_ckti,fixed-factor-clock|21?LW3]3dpll4_m4x2_ck@d00ti,gate-clock|3x LW]dpll4_m5_ck@f40ti,divider-clock|?x@W4]4dpll4_m5x2_mul_ckti,fixed-factor-clock|41?LW5]5dpll4_m5x2_ck@d00ti,hsdiv-gate-clock|5x LWk]kdpll4_m6_ck@1140ti,divider-clock|?x@W6]6dpll4_m6x2_mul_ckfixed-factor-clock|6W7]7dpll4_m6x2_ck@d00ti,hsdiv-gate-clock|7x W8]8emu_per_alwon_ckfixed-factor-clock|8Wd]dclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock|'x pW:]:clkout2_src_mux_ck@d70ti,composite-mux-clock|'+9x pW;];clkout2_src_ckti,composite-clock|:;W<]<sys_clkout2@d70ti,divider-clock|<@x p_mpu_ckfixed-factor-clock|=W>]>arm_fck@924ti,divider-clock|>x $emu_mpu_alwon_ckfixed-factor-clock|>We]el3_ick@a40ti,divider-clock|'x @W?]?l4_ick@a40ti,divider-clock|?x @W@]@rm_ick@c40ti,divider-clock|@x @gpt10_gate_fck@a00ti,composite-gate-clock| x WB]Bgpt10_mux_fck@a40ti,composite-mux-clock|Ax @WC]Cgpt10_fckti,composite-clock|BCgpt11_gate_fck@a00ti,composite-gate-clock| x WD]Dgpt11_mux_fck@a40ti,composite-mux-clock|Ax @WE]Egpt11_fckti,composite-clock|DEcore_96m_fckfixed-factor-clock|FW]mmchs2_fck@a00ti,wait-gate-clock|x W]mmchs1_fck@a00ti,wait-gate-clock|x W]i2c3_fck@a00ti,wait-gate-clock|x W]i2c2_fck@a00ti,wait-gate-clock|x W]i2c1_fck@a00ti,wait-gate-clock|x W]mcbsp5_gate_fck@a00ti,composite-gate-clock| x W]mcbsp1_gate_fck@a00ti,composite-gate-clock| x W ] core_48m_fckfixed-factor-clock|1WG]Gmcspi4_fck@a00ti,wait-gate-clock|Gx W]mcspi3_fck@a00ti,wait-gate-clock|Gx W]mcspi2_fck@a00ti,wait-gate-clock|Gx W]mcspi1_fck@a00ti,wait-gate-clock|Gx W]uart2_fck@a00ti,wait-gate-clock|Gx W]uart1_fck@a00ti,wait-gate-clock|Gx  W]core_12m_fckfixed-factor-clock|HWI]Ihdq_fck@a00ti,wait-gate-clock|Ix W]core_l3_ickfixed-factor-clock|?WJ]Jsdrc_ick@a10ti,wait-gate-clock|Jx W]gpmc_fckfixed-factor-clock|Jcore_l4_ickfixed-factor-clock|@WK]Kmmchs2_ick@a10ti,omap3-interface-clock|Kx W]mmchs1_ick@a10ti,omap3-interface-clock|Kx W]hdq_ick@a10ti,omap3-interface-clock|Kx W]mcspi4_ick@a10ti,omap3-interface-clock|Kx W]mcspi3_ick@a10ti,omap3-interface-clock|Kx W]mcspi2_ick@a10ti,omap3-interface-clock|Kx W]mcspi1_ick@a10ti,omap3-interface-clock|Kx W]i2c3_ick@a10ti,omap3-interface-clock|Kx W]i2c2_ick@a10ti,omap3-interface-clock|Kx W]i2c1_ick@a10ti,omap3-interface-clock|Kx W]uart2_ick@a10ti,omap3-interface-clock|Kx W]uart1_ick@a10ti,omap3-interface-clock|Kx  W]gpt11_ick@a10ti,omap3-interface-clock|Kx  W]gpt10_ick@a10ti,omap3-interface-clock|Kx  W]mcbsp5_ick@a10ti,omap3-interface-clock|Kx  W]mcbsp1_ick@a10ti,omap3-interface-clock|Kx  W]omapctrl_ick@a10ti,omap3-interface-clock|Kx W]dss_tv_fck@e00ti,gate-clock|9xW]dss_96m_fck@e00ti,gate-clock|FxW]dss2_alwon_fck@e00ti,gate-clock|xW]dummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock|x WL]Lgpt1_mux_fck@c40ti,composite-mux-clock|Ax @WM]Mgpt1_fckti,composite-clock|LMaes2_ick@a10ti,omap3-interface-clock|Kx W]wkup_32k_fckfixed-factor-clock|AWN]Ngpio1_dbck@c00ti,gate-clock|Nx W]sha12_ick@a10ti,omap3-interface-clock|Kx W]wdt2_fck@c00ti,wait-gate-clock|Nx W]wdt2_ick@c10ti,omap3-interface-clock|Ox W]wdt1_ick@c10ti,omap3-interface-clock|Ox W]gpio1_ick@c10ti,omap3-interface-clock|Ox W]omap_32ksync_ick@c10ti,omap3-interface-clock|Ox W]gpt12_ick@c10ti,omap3-interface-clock|Ox W]gpt1_ick@c10ti,omap3-interface-clock|Ox W]per_96m_fckfixed-factor-clock|*W ] per_48m_fckfixed-factor-clock|1WP]Puart3_fck@1000ti,wait-gate-clock|Px W]gpt2_gate_fck@1000ti,composite-gate-clock|xWQ]Qgpt2_mux_fck@1040ti,composite-mux-clock|Ax@WR]Rgpt2_fckti,composite-clock|QRgpt3_gate_fck@1000ti,composite-gate-clock|xWS]Sgpt3_mux_fck@1040ti,composite-mux-clock|Ax@WT]Tgpt3_fckti,composite-clock|STgpt4_gate_fck@1000ti,composite-gate-clock|xWU]Ugpt4_mux_fck@1040ti,composite-mux-clock|Ax@WV]Vgpt4_fckti,composite-clock|UVgpt5_gate_fck@1000ti,composite-gate-clock|xWW]Wgpt5_mux_fck@1040ti,composite-mux-clock|Ax@WX]Xgpt5_fckti,composite-clock|WXgpt6_gate_fck@1000ti,composite-gate-clock|xWY]Ygpt6_mux_fck@1040ti,composite-mux-clock|Ax@WZ]Zgpt6_fckti,composite-clock|YZgpt7_gate_fck@1000ti,composite-gate-clock|xW[][gpt7_mux_fck@1040ti,composite-mux-clock|Ax@W\]\gpt7_fckti,composite-clock|[\gpt8_gate_fck@1000ti,composite-gate-clock| xW]]]gpt8_mux_fck@1040ti,composite-mux-clock|Ax@W^]^gpt8_fckti,composite-clock|]^gpt9_gate_fck@1000ti,composite-gate-clock| xW_]_gpt9_mux_fck@1040ti,composite-mux-clock|Ax@W`]`gpt9_fckti,composite-clock|_`per_32k_alwon_fckfixed-factor-clock|AWa]agpio6_dbck@1000ti,gate-clock|axW]gpio5_dbck@1000ti,gate-clock|axW]gpio4_dbck@1000ti,gate-clock|axW]gpio3_dbck@1000ti,gate-clock|axW]gpio2_dbck@1000ti,gate-clock|ax W]wdt3_fck@1000ti,wait-gate-clock|ax W]per_l4_ickfixed-factor-clock|@Wb]bgpio6_ick@1010ti,omap3-interface-clock|bxW]gpio5_ick@1010ti,omap3-interface-clock|bxW]gpio4_ick@1010ti,omap3-interface-clock|bxW]gpio3_ick@1010ti,omap3-interface-clock|bxW]gpio2_ick@1010ti,omap3-interface-clock|bx W]wdt3_ick@1010ti,omap3-interface-clock|bx W]uart3_ick@1010ti,omap3-interface-clock|bx W]uart4_ick@1010ti,omap3-interface-clock|bxW]gpt9_ick@1010ti,omap3-interface-clock|bx W]gpt8_ick@1010ti,omap3-interface-clock|bx W]gpt7_ick@1010ti,omap3-interface-clock|bxW]gpt6_ick@1010ti,omap3-interface-clock|bxW]gpt5_ick@1010ti,omap3-interface-clock|bxW]gpt4_ick@1010ti,omap3-interface-clock|bxW]gpt3_ick@1010ti,omap3-interface-clock|bxW]gpt2_ick@1010ti,omap3-interface-clock|bxW]mcbsp2_ick@1010ti,omap3-interface-clock|bxW]mcbsp3_ick@1010ti,omap3-interface-clock|bxW]mcbsp4_ick@1010ti,omap3-interface-clock|bxW]mcbsp2_gate_fck@1000ti,composite-gate-clock|xW ] mcbsp3_gate_fck@1000ti,composite-gate-clock|xW]mcbsp4_gate_fck@1000ti,composite-gate-clock|xW]emu_src_mux_ck@1140 ti,mux-clock|cdex@Wf]femu_src_ckti,clkdm-gate-clock|fWg]gpclk_fck@1140ti,divider-clock|gx@pclkx2_fck@1140ti,divider-clock|gx@atclk_fck@1140ti,divider-clock|gx@traceclk_src_fck@1140 ti,mux-clock|cdex@Wh]htraceclk_fck@1140ti,divider-clock|h x@secure_32k_fck fixed-clockWi]igpt12_fckfixed-factor-clock|iwdt1_fckfixed-factor-clock|isecurity_l4_ick2fixed-factor-clock|@Wj]jaes1_ick@a14ti,omap3-interface-clock|jx rng_ick@a14ti,omap3-interface-clock|jx sha11_ick@a14ti,omap3-interface-clock|jx des1_ick@a14ti,omap3-interface-clock|jx cam_mclk@f00ti,gate-clock|kxLcam_ick@f10!ti,omap3-no-wait-interface-clock|@xW]csi2_96m_fck@f00ti,gate-clock|xW]security_l3_ickfixed-factor-clock|?Wl]lpka_ick@a14ti,omap3-interface-clock|lx icr_ick@a10ti,omap3-interface-clock|Kx des2_ick@a10ti,omap3-interface-clock|Kx mspro_ick@a10ti,omap3-interface-clock|Kx mailboxes_ick@a10ti,omap3-interface-clock|Kx ssi_l4_ickfixed-factor-clock|@Ws]ssr1_fck@c00ti,wait-gate-clock|x sr2_fck@c00ti,wait-gate-clock|x sr_l4_ickfixed-factor-clock|@dpll2_fck@40ti,divider-clock|'x@Wm]mdpll2_ck@4ti,omap3-dpll-clock|mx$@4uWn]ndpll2_m2_ck@44ti,divider-clock|nxDWo]oiva2_ck@0ti,wait-gate-clock|oxW]modem_fck@a00ti,omap3-interface-clock|x W]sad2d_ick@a10ti,omap3-interface-clock|?x W]mad2d_ick@a18ti,omap3-interface-clock|?x W]mspro_fck@a00ti,wait-gate-clock|x ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock| x Wp]pssi_ssr_div_fck_3430es2@a40ti,composite-divider-clock| x @$Wq]qssi_ssr_fck_3430es2ti,composite-clock|pqWr]rssi_sst_fck_3430es2fixed-factor-clock|rW]hsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clock|Jx W]ssi_ick_3430es2@a10ti,omap3-ssi-interface-clock|sx W ] usim_gate_fck@c00ti,composite-gate-clock|F x W~]~sys_d2_ckfixed-factor-clock|Wu]uomap_96m_d2_fckfixed-factor-clock|FWv]vomap_96m_d4_fckfixed-factor-clock|FWw]womap_96m_d8_fckfixed-factor-clock|FWx]xomap_96m_d10_fckfixed-factor-clock|F Wy]ydpll5_m2_d4_ckfixed-factor-clock|tWz]zdpll5_m2_d8_ckfixed-factor-clock|tW{]{dpll5_m2_d16_ckfixed-factor-clock|tW|]|dpll5_m2_d20_ckfixed-factor-clock|tW}]}usim_mux_fck@c40ti,composite-mux-clock(|uvwxyz{|}x @W]usim_fckti,composite-clock|~usim_ick@c10ti,omap3-interface-clock|Ox  W]dpll5_ck@d04ti,omap3-dpll-clock|x  $ L 4uW]dpll5_m2_ck@d50ti,divider-clock|x PWt]tsgx_gate_fck@b00ti,composite-gate-clock|'x W]core_d3_ckfixed-factor-clock|'W]core_d4_ckfixed-factor-clock|'W]core_d6_ckfixed-factor-clock|'W]omap_192m_alwon_fckfixed-factor-clock|#W]core_d2_ckfixed-factor-clock|'W]sgx_mux_fck@b40ti,composite-mux-clock |+x @W]sgx_fckti,composite-clock|sgx_ick@b10ti,wait-gate-clock|?x W]cpefuse_fck@a08ti,gate-clock|x W]ts_fck@a08ti,gate-clock|Ax W]usbtll_fck@a08ti,wait-gate-clock|tx W]usbtll_ick@a18ti,omap3-interface-clock|Kx W]mmchs3_ick@a10ti,omap3-interface-clock|Kx W]mmchs3_fck@a00ti,wait-gate-clock|x W]dss1_alwon_fck_3430es2@e00ti,dss-gate-clock|xLW]dss_ick_3430es2@e10ti,omap3-dss-interface-clock|@xW]usbhost_120m_fck@1400ti,gate-clock|txW]usbhost_48m_fck@1400ti,dss-gate-clock|1xW]usbhost_ick@1410ti,omap3-dss-interface-clock|@xW]uart4_fck@1000ti,wait-gate-clock|PxW]clockdomainscore_l3_clkdmti,clockdomain|dpll3_clkdmti,clockdomain|dpll1_clkdmti,clockdomain|per_clkdmti,clockdomainl|emu_clkdmti,clockdomain|gdpll4_clkdmti,clockdomain|wkup_clkdmti,clockdomain$|dss_clkdmti,clockdomain|core_l4_clkdmti,clockdomain|cam_clkdmti,clockdomain|iva2_clkdmti,clockdomain|dpll2_clkdmti,clockdomain|nd2d_clkdmti,clockdomain |dpll5_clkdmti,clockdomain|sgx_clkdmti,clockdomain|usbhost_clkdmti,clockdomain |counter@48320000ti,omap-counter32kxH2  counter_32kinterrupt-controller@48200000ti,omap3-intcxH W]dma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaxH`  `W]gpio@48310000ti,omap3-gpioxH1gpio1W]gpio@49050000ti,omap3-gpioxIgpio2gpio@49052000ti,omap3-gpioxI gpio3gpio@49054000ti,omap3-gpioxI@ gpio4gpio@49056000ti,omap3-gpioxI`!gpio5W]gpio@49058000ti,omap3-gpioxI"gpio6W]serial@4806a000ti,omap3-uartxH H12txrxuart1l+default9serial@4806c000ti,omap3-uartxHI34txrxuart2l+default9serial@49020000ti,omap3-uartxIJ56txrxuart3l+default9i2c@48070000 ti,omap3-i2cxH8txrx+i2c1+default9'@twl@48xH  ti,twl4030+default9audioti,twl4030-audiocodecrtcti,twl4030-rtc bciti,twl4030-bci watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1{ ' regulator-vdacti,twl4030-vdac{w@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1{:0W]regulator-vmmc2ti,twl4030-vmmc2{:0regulator-vusb1v5ti,twl4030-vusb1v5W]regulator-vusb1v8ti,twl4030-vusb1v8W]regulator-vusb3v1ti,twl4030-vusb3v1W]regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2{w@w@ lvdds_dsiregulator-vsimti,twl4030-vsim{w@-W]gpioti,twl4030-gpio$W]twl4030-usbti,twl4030-usb 0>LZcW]pwmti,twl4030-pwmnpwmledti,twl4030-pwmlednpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadymadcti,twl4030-madci2c@48072000 ti,omap3-i2cxH 9txrx+i2c2i2c@48060000 ti,omap3-i2cxH=txrx+i2c3+default9W]eeprom@50 ti,eepromxPmailbox@48094000ti,omap3-mailboxmailboxxH @dsp  spi@48098000ti,omap2-mcspixH A+mcspi1@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspixH B+mcspi2 +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspixH [+mcspi3 tx0rx0tx1rx1spi@480ba000ti,omap2-mcspixH 0+mcspi4FGtx0rx01w@480b2000 ti,omap3-1wxH :hdq1wmmc@4809c000ti,omap3-hsmmcxH Smmc1=>txrx+default9(8 B Kmmc@480b4000ti,omap3-hsmmcxH @Vmmc2/0txrx+default9T8_mmc@480ad000ti,omap3-hsmmcxH ^mmc3MNtxrx mdisabledmmu@480bd400tti,omap2-iommuxH mmu_ispW ] mmu@5d000000tti,omap2-iommux]mmu_iva mdisabledwdt@48314000 ti,omap3-wdtxH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspxH@mpu ;< commontxrxmcbsp1 txrx|fck mdisabledmcbsp@49022000ti,omap3-mcbspxI I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrx|fckickmokay+default9W ] mcbsp@49024000ti,omap3-mcbspxI@I mpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetonetxrx|fckick mdisabledmcbsp@49026000ti,omap3-mcbspxI`mpu 67 commontxrxmcbsp4txrx|fck mdisabledmcbsp@48096000ti,omap3-mcbspxH `mpu QR commontxrxmcbsp5txrx|fck mdisabledsham@480c3000ti,omap3-shamshamxH 0d1Erxsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_corexH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivaxH timer@48318000ti,omap3430-timerxH1%timer1timer@49032000ti,omap3430-timerxI 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lvddvario<W]regulator-vdd33aregulator-fixedlvdd33a<W]leds+default9  gpio-ledsbootRomap3:green:boot EPonuser0Romap3:red:user0 EPoffuser1Romap3:red:user1 EPoffuser2Romap3:green:user1 Ehsusb1_power_regregulator-fixed lhsusb1_vbus{2Z2Z ^cpW]hsusb1_phyusb-nop-xceiv tW]encoder ti,tfp410  ports+port@0xendpointW]port@1xendpointW]connectordvi-connectorRdviportendpointW]fixedregulator-mmcsdioregulator-fixedlvmmcsdio_fixed{2Z2ZW]mmc2_pwrseqmmc-pwrseq-simplet  W] compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyoperating-pointsinterruptsti,hwmodsranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinslinux,phandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplyvmmc_aux-supplybus-widthcd-gpioswp-gpiosmmc-pwrseqnon-removablestatus#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport1-modephysgpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthgpmc,mux-add-datagpmc,oe-on-nsgpmc,we-on-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsenvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerremote-endpointdata-linesti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-type#thermal-sensor-cellsstdout-pathti,modelti,mcbspregulator-always-ondefault-stategpiostartup-delay-usreset-gpiosvcc-supplypowerdown-gpiosdigitalddc-i2c-bus