8$(ti,omap3-ldpti,omap3 +!7TI OMAP3430 LDP (Zoom1 Labrador)aliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000 d/displaycpus+cpu@0arm,cortex-a8mcpuy}cpu(HАg8 Odp` 'ppmu@54000000arm,cortex-a8-pmuyTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busyh +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busy + pinmux@30 ti,omap3-padconfpinctrl-singley08+8>pinmux_twl4030_pinsFA8>pinmux_gpio_key_pinsHF8>pinmux_musb_pins`Frz|~vxt8>pinmux_mmc1_pins0F8>scm_conf@270sysconsimple-busyp0+ p08>pbias_regulator@2b0ti,pbias-omap3ti,pbias-omapyZpbias_mmc_omap2430apbias_mmc_omap2430pw@-8>clocks+mcbsp5_mux_fck@68ti,composite-mux-clock}yh8>mcbsp5_fckti,composite-clock}8>mcbsp1_mux_fck@4ti,composite-mux-clock}y8 > mcbsp1_fckti,composite-clock} 8>mcbsp2_mux_fck@4ti,composite-mux-clock} y8 > mcbsp2_fckti,composite-clock} 8>mcbsp3_mux_fck@68ti,composite-mux-clock} yh8>mcbsp3_fckti,composite-clock}8>mcbsp4_mux_fck@68ti,composite-mux-clock} yh8>mcbsp4_fckti,composite-clock}8>clockdomainspinmux@a00 ti,omap3-padconfpinctrl-singley \+pinmux_twl4030_vpins F8>aes@480c5000 ti,omap3-aesaesyH PPABtxrxprm@48306000 ti,omap3-prmyH0`@ clocks+virt_16_8m_ck fixed-clockY8>osc_sys_ck@d40 ti,mux-clock}y @8>sys_ck@1270ti,divider-clock}yp8>sys_clkout1@d70ti,gate-clock}y pdpll3_x2_ckfixed-factor-clock}dpll3_m2x2_ckfixed-factor-clock}8>dpll4_x2_ckfixed-factor-clock}corex2_fckfixed-factor-clock}8>wkup_l4_ickfixed-factor-clock}8N>Ncorex2_d3_fckfixed-factor-clock}8>corex2_d5_fckfixed-factor-clock}8>clockdomainscm@48004000 ti,omap3-cmyH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clock8@>@virt_12m_ck fixed-clock8>virt_13m_ck fixed-clock]@8>virt_19200000_ck fixed-clock$8>virt_26000000_ck fixed-clock8>virt_38_4m_ck fixed-clockI8>dpll4_ck@d00ti,omap3-dpll-per-clock}y D 08>dpll4_m2_ck@d48ti,divider-clock}?y H8 > dpll4_m2x2_mul_ckfixed-factor-clock} 8!>!dpll4_m2x2_ck@d00ti,gate-clock}!y 8">"omap_96m_alwon_fckfixed-factor-clock}"8)>)dpll3_ck@d00ti,omap3-dpll-core-clock}y @ 08>dpll3_m3_ck@1140ti,divider-clock}y@8#>#dpll3_m3x2_mul_ckfixed-factor-clock}#8$>$dpll3_m3x2_ck@d00ti,gate-clock}$ y 8%>%emu_core_alwon_ckfixed-factor-clock}%8b>bsys_altclk fixed-clock8.>.mcbsp_clks fixed-clock8>dpll3_m2_ck@d40ti,divider-clock}y @8>core_ckfixed-factor-clock}8&>&dpll1_fck@940ti,divider-clock}&y @8'>'dpll1_ck@904ti,omap3-dpll-clock}'y  $ @ 48>dpll1_x2_ckfixed-factor-clock}8(>(dpll1_x2m2_ck@944ti,divider-clock}(y D8<><cm_96m_fckfixed-factor-clock})8*>*omap_96m_fck@d40 ti,mux-clock}*y @8E>Edpll4_m3_ck@e40ti,divider-clock} y@8+>+dpll4_m3x2_mul_ckfixed-factor-clock}+8,>,dpll4_m3x2_ck@d00ti,gate-clock},y 8->-omap_54m_fck@d40 ti,mux-clock}-.y @88>8cm_96m_d2_fckfixed-factor-clock}*8/>/omap_48m_fck@d40 ti,mux-clock}/.y @80>0omap_12m_fckfixed-factor-clock}08G>Gdpll4_m4_ck@e40ti,divider-clock} y@81>1dpll4_m4x2_mul_ckti,fixed-factor-clock}1&4A82>2dpll4_m4x2_ck@d00ti,gate-clock}2y A8>dpll4_m5_ck@f40ti,divider-clock}?y@83>3dpll4_m5x2_mul_ckti,fixed-factor-clock}3&4A84>4dpll4_m5x2_ck@d00ti,gate-clock}4y A8j>jdpll4_m6_ck@1140ti,divider-clock}?y@85>5dpll4_m6x2_mul_ckfixed-factor-clock}586>6dpll4_m6x2_ck@d00ti,gate-clock}6y 87>7emu_per_alwon_ckfixed-factor-clock}78c>cclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock}&y p89>9clkout2_src_mux_ck@d70ti,composite-mux-clock}&*8y p8:>:clkout2_src_ckti,composite-clock}9:8;>;sys_clkout2@d70ti,divider-clock};@y pTmpu_ckfixed-factor-clock}<8=>=arm_fck@924ti,divider-clock}=y $emu_mpu_alwon_ckfixed-factor-clock}=8d>dl3_ick@a40ti,divider-clock}&y @8>>>l4_ick@a40ti,divider-clock}>y @8?>?rm_ick@c40ti,divider-clock}?y @gpt10_gate_fck@a00ti,composite-gate-clock} y 8A>Agpt10_mux_fck@a40ti,composite-mux-clock}@y @8B>Bgpt10_fckti,composite-clock}ABgpt11_gate_fck@a00ti,composite-gate-clock} y 8C>Cgpt11_mux_fck@a40ti,composite-mux-clock}@y @8D>Dgpt11_fckti,composite-clock}CDcore_96m_fckfixed-factor-clock}E8>mmchs2_fck@a00ti,wait-gate-clock}y 8>mmchs1_fck@a00ti,wait-gate-clock}y 8>i2c3_fck@a00ti,wait-gate-clock}y 8>i2c2_fck@a00ti,wait-gate-clock}y 8>i2c1_fck@a00ti,wait-gate-clock}y 8>mcbsp5_gate_fck@a00ti,composite-gate-clock} y 8>mcbsp1_gate_fck@a00ti,composite-gate-clock} y 8 > core_48m_fckfixed-factor-clock}08F>Fmcspi4_fck@a00ti,wait-gate-clock}Fy 8>mcspi3_fck@a00ti,wait-gate-clock}Fy 8>mcspi2_fck@a00ti,wait-gate-clock}Fy 8>mcspi1_fck@a00ti,wait-gate-clock}Fy 8>uart2_fck@a00ti,wait-gate-clock}Fy 8>uart1_fck@a00ti,wait-gate-clock}Fy  8>core_12m_fckfixed-factor-clock}G8H>Hhdq_fck@a00ti,wait-gate-clock}Hy 8>core_l3_ickfixed-factor-clock}>8I>Isdrc_ick@a10ti,wait-gate-clock}Iy 8>gpmc_fckfixed-factor-clock}Icore_l4_ickfixed-factor-clock}?8J>Jmmchs2_ick@a10ti,omap3-interface-clock}Jy 8>mmchs1_ick@a10ti,omap3-interface-clock}Jy 8>hdq_ick@a10ti,omap3-interface-clock}Jy 8>mcspi4_ick@a10ti,omap3-interface-clock}Jy 8>mcspi3_ick@a10ti,omap3-interface-clock}Jy 8>mcspi2_ick@a10ti,omap3-interface-clock}Jy 8>mcspi1_ick@a10ti,omap3-interface-clock}Jy 8>i2c3_ick@a10ti,omap3-interface-clock}Jy 8>i2c2_ick@a10ti,omap3-interface-clock}Jy 8>i2c1_ick@a10ti,omap3-interface-clock}Jy 8>uart2_ick@a10ti,omap3-interface-clock}Jy 8>uart1_ick@a10ti,omap3-interface-clock}Jy  8>gpt11_ick@a10ti,omap3-interface-clock}Jy  8>gpt10_ick@a10ti,omap3-interface-clock}Jy  8>mcbsp5_ick@a10ti,omap3-interface-clock}Jy  8>mcbsp1_ick@a10ti,omap3-interface-clock}Jy  8>omapctrl_ick@a10ti,omap3-interface-clock}Jy 8>dss_tv_fck@e00ti,gate-clock}8y8>dss_96m_fck@e00ti,gate-clock}Ey8>dss2_alwon_fck@e00ti,gate-clock}y8>dummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock}y 8K>Kgpt1_mux_fck@c40ti,composite-mux-clock}@y @8L>Lgpt1_fckti,composite-clock}KLaes2_ick@a10ti,omap3-interface-clock}Jy 8>wkup_32k_fckfixed-factor-clock}@8M>Mgpio1_dbck@c00ti,gate-clock}My 8>sha12_ick@a10ti,omap3-interface-clock}Jy 8>wdt2_fck@c00ti,wait-gate-clock}My 8>wdt2_ick@c10ti,omap3-interface-clock}Ny 8>wdt1_ick@c10ti,omap3-interface-clock}Ny 8>gpio1_ick@c10ti,omap3-interface-clock}Ny 8>omap_32ksync_ick@c10ti,omap3-interface-clock}Ny 8>gpt12_ick@c10ti,omap3-interface-clock}Ny 8>gpt1_ick@c10ti,omap3-interface-clock}Ny 8>per_96m_fckfixed-factor-clock})8 > per_48m_fckfixed-factor-clock}08O>Ouart3_fck@1000ti,wait-gate-clock}Oy 8>gpt2_gate_fck@1000ti,composite-gate-clock}y8P>Pgpt2_mux_fck@1040ti,composite-mux-clock}@y@8Q>Qgpt2_fckti,composite-clock}PQgpt3_gate_fck@1000ti,composite-gate-clock}y8R>Rgpt3_mux_fck@1040ti,composite-mux-clock}@y@8S>Sgpt3_fckti,composite-clock}RSgpt4_gate_fck@1000ti,composite-gate-clock}y8T>Tgpt4_mux_fck@1040ti,composite-mux-clock}@y@8U>Ugpt4_fckti,composite-clock}TUgpt5_gate_fck@1000ti,composite-gate-clock}y8V>Vgpt5_mux_fck@1040ti,composite-mux-clock}@y@8W>Wgpt5_fckti,composite-clock}VWgpt6_gate_fck@1000ti,composite-gate-clock}y8X>Xgpt6_mux_fck@1040ti,composite-mux-clock}@y@8Y>Ygpt6_fckti,composite-clock}XYgpt7_gate_fck@1000ti,composite-gate-clock}y8Z>Zgpt7_mux_fck@1040ti,composite-mux-clock}@y@8[>[gpt7_fckti,composite-clock}Z[gpt8_gate_fck@1000ti,composite-gate-clock} y8\>\gpt8_mux_fck@1040ti,composite-mux-clock}@y@8]>]gpt8_fckti,composite-clock}\]gpt9_gate_fck@1000ti,composite-gate-clock} y8^>^gpt9_mux_fck@1040ti,composite-mux-clock}@y@8_>_gpt9_fckti,composite-clock}^_per_32k_alwon_fckfixed-factor-clock}@8`>`gpio6_dbck@1000ti,gate-clock}`y8>gpio5_dbck@1000ti,gate-clock}`y8>gpio4_dbck@1000ti,gate-clock}`y8>gpio3_dbck@1000ti,gate-clock}`y8>gpio2_dbck@1000ti,gate-clock}`y 8>wdt3_fck@1000ti,wait-gate-clock}`y 8>per_l4_ickfixed-factor-clock}?8a>agpio6_ick@1010ti,omap3-interface-clock}ay8>gpio5_ick@1010ti,omap3-interface-clock}ay8>gpio4_ick@1010ti,omap3-interface-clock}ay8>gpio3_ick@1010ti,omap3-interface-clock}ay8>gpio2_ick@1010ti,omap3-interface-clock}ay 8>wdt3_ick@1010ti,omap3-interface-clock}ay 8>uart3_ick@1010ti,omap3-interface-clock}ay 8>uart4_ick@1010ti,omap3-interface-clock}ay8>gpt9_ick@1010ti,omap3-interface-clock}ay 8>gpt8_ick@1010ti,omap3-interface-clock}ay 8>gpt7_ick@1010ti,omap3-interface-clock}ay8>gpt6_ick@1010ti,omap3-interface-clock}ay8>gpt5_ick@1010ti,omap3-interface-clock}ay8>gpt4_ick@1010ti,omap3-interface-clock}ay8>gpt3_ick@1010ti,omap3-interface-clock}ay8>gpt2_ick@1010ti,omap3-interface-clock}ay8>mcbsp2_ick@1010ti,omap3-interface-clock}ay8>mcbsp3_ick@1010ti,omap3-interface-clock}ay8>mcbsp4_ick@1010ti,omap3-interface-clock}ay8>mcbsp2_gate_fck@1000ti,composite-gate-clock}y8 > mcbsp3_gate_fck@1000ti,composite-gate-clock}y8>mcbsp4_gate_fck@1000ti,composite-gate-clock}y8>emu_src_mux_ck@1140 ti,mux-clock}bcdy@8e>eemu_src_ckti,clkdm-gate-clock}e8f>fpclk_fck@1140ti,divider-clock}fy@pclkx2_fck@1140ti,divider-clock}fy@atclk_fck@1140ti,divider-clock}fy@traceclk_src_fck@1140 ti,mux-clock}bcdy@8g>gtraceclk_fck@1140ti,divider-clock}g y@secure_32k_fck fixed-clock8h>hgpt12_fckfixed-factor-clock}hwdt1_fckfixed-factor-clock}hsecurity_l4_ick2fixed-factor-clock}?8i>iaes1_ick@a14ti,omap3-interface-clock}iy rng_ick@a14ti,omap3-interface-clock}iy sha11_ick@a14ti,omap3-interface-clock}iy des1_ick@a14ti,omap3-interface-clock}iy cam_mclk@f00ti,gate-clock}jyAcam_ick@f10!ti,omap3-no-wait-interface-clock}?y8>csi2_96m_fck@f00ti,gate-clock}y8>security_l3_ickfixed-factor-clock}>8k>kpka_ick@a14ti,omap3-interface-clock}ky icr_ick@a10ti,omap3-interface-clock}Jy des2_ick@a10ti,omap3-interface-clock}Jy mspro_ick@a10ti,omap3-interface-clock}Jy mailboxes_ick@a10ti,omap3-interface-clock}Jy ssi_l4_ickfixed-factor-clock}?8r>rsr1_fck@c00ti,wait-gate-clock}y sr2_fck@c00ti,wait-gate-clock}y sr_l4_ickfixed-factor-clock}?dpll2_fck@40ti,divider-clock}&y@8l>ldpll2_ck@4ti,omap3-dpll-clock}ly$@4j|8m>mdpll2_m2_ck@44ti,divider-clock}myD8n>niva2_ck@0ti,wait-gate-clock}ny8>modem_fck@a00ti,omap3-interface-clock}y 8>sad2d_ick@a10ti,omap3-interface-clock}>y 8>mad2d_ick@a18ti,omap3-interface-clock}>y 8>mspro_fck@a00ti,wait-gate-clock}y ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock}y 8o>ossi_ssr_div_fck_3430es2@a40ti,composite-divider-clock}y @$8p>pssi_ssr_fck_3430es2ti,composite-clock}op8q>qssi_sst_fck_3430es2fixed-factor-clock}q8>hsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clock}Iy 8>ssi_ick_3430es2@a10ti,omap3-ssi-interface-clock}ry 8>usim_gate_fck@c00ti,composite-gate-clock}E y 8}>}sys_d2_ckfixed-factor-clock}8t>tomap_96m_d2_fckfixed-factor-clock}E8u>uomap_96m_d4_fckfixed-factor-clock}E8v>vomap_96m_d8_fckfixed-factor-clock}E8w>womap_96m_d10_fckfixed-factor-clock}E 8x>xdpll5_m2_d4_ckfixed-factor-clock}s8y>ydpll5_m2_d8_ckfixed-factor-clock}s8z>zdpll5_m2_d16_ckfixed-factor-clock}s8{>{dpll5_m2_d20_ckfixed-factor-clock}s8|>|usim_mux_fck@c40ti,composite-mux-clock(}tuvwxyz{|y @8~>~usim_fckti,composite-clock}}~usim_ick@c10ti,omap3-interface-clock}Ny  8>dpll5_ck@d04ti,omap3-dpll-clock}y  $ L 4j|8>dpll5_m2_ck@d50ti,divider-clock}y P8s>ssgx_gate_fck@b00ti,composite-gate-clock}&y 8>core_d3_ckfixed-factor-clock}&8>core_d4_ckfixed-factor-clock}&8>core_d6_ckfixed-factor-clock}&8>omap_192m_alwon_fckfixed-factor-clock}"8>core_d2_ckfixed-factor-clock}&8>sgx_mux_fck@b40ti,composite-mux-clock }*y @8>sgx_fckti,composite-clock}sgx_ick@b10ti,wait-gate-clock}>y 8>cpefuse_fck@a08ti,gate-clock}y 8>ts_fck@a08ti,gate-clock}@y 8>usbtll_fck@a08ti,wait-gate-clock}sy 8>usbtll_ick@a18ti,omap3-interface-clock}Jy 8>mmchs3_ick@a10ti,omap3-interface-clock}Jy 8>mmchs3_fck@a00ti,wait-gate-clock}y 8>dss1_alwon_fck_3430es2@e00ti,dss-gate-clock}yA8>dss_ick_3430es2@e10ti,omap3-dss-interface-clock}?y8>usbhost_120m_fck@1400ti,gate-clock}sy8>usbhost_48m_fck@1400ti,dss-gate-clock}0y8>usbhost_ick@1410ti,omap3-dss-interface-clock}?y8>clockdomainscore_l3_clkdmti,clockdomain}dpll3_clkdmti,clockdomain}dpll1_clkdmti,clockdomain}per_clkdmti,clockdomainh}emu_clkdmti,clockdomain}fdpll4_clkdmti,clockdomain}wkup_clkdmti,clockdomain$}dss_clkdmti,clockdomain}core_l4_clkdmti,clockdomain}cam_clkdmti,clockdomain}iva2_clkdmti,clockdomain}dpll2_clkdmti,clockdomain}md2d_clkdmti,clockdomain }dpll5_clkdmti,clockdomain}sgx_clkdmti,clockdomain}usbhost_clkdmti,clockdomain }counter@48320000ti,omap-counter32kyH2  counter_32kinterrupt-controller@48200000ti,omap3-intcyH 8>dma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmayH`  `8>gpio@48310000ti,omap3-gpioyH1gpio1gpio@49050000ti,omap3-gpioyIgpio28>gpio@49052000ti,omap3-gpioyI gpio3gpio@49054000ti,omap3-gpioyI@ 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8>regulator-vdacti,twl4030-vdacpw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1p:08>regulator-vmmc2ti,twl4030-vmmc2p:0regulator-vusb1v5ti,twl4030-vusb1v58>regulator-vusb1v8ti,twl4030-vusb1v88>regulator-vusb3v1ti,twl4030-vusb3v18>regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2pw@w@Aregulator-vsimti,twl4030-vsimpw@-gpioti,twl4030-gpio8>twl4030-usbti,twl4030-usb Ucq8>pwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadD?  @A Bsrmadcti,twl4030-madci2c@48072000 ti,omap3-i2cyH 9txrx+i2c2i2c@48060000 ti,omap3-i2cyH=txrx+i2c3mailbox@48094000ti,omap3-mailboxmailboxyH @dsp  spi@48098000ti,omap2-mcspiyH A+mcspi1&@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3tsc2046@0y ti,tsc20464B@FQZ@clu(  spi@4809a000ti,omap2-mcspiyH B+mcspi2& +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiyH [+mcspi3& tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiyH 0+mcspi4&FGtx0rx01w@480b2000 ti,omap3-1wyH :hdq1wmmc@4809c000ti,omap3-pre-es3-hsmmcyH Smmc1=>txrx defaultmmc@480b4000ti,omap3-hsmmcyH @Vmmc2/0txrx disabledmmc@480ad000ti,omap3-hsmmcyH ^mmc3MNtxrx disabledmmu@480bd400ti,omap2-iommuyH mmu_isp8>mmu@5d000000ti,omap2-iommuy]mmu_iva disabledwdt@48314000 ti,omap3-wdtyH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspyH@mpu ;< commontxrx)mcbsp1 txrx}fck disabledmcbsp@49022000ti,omap3-mcbspyI I mpusidetone>?commontxrxsidetone)mcbsp2mcbsp2_sidetone!"txrx}fckick disabledmcbsp@49024000ti,omap3-mcbspyI@I mpusidetoneYZcommontxrxsidetone)mcbsp3mcbsp3_sidetonetxrx}fckick disabledmcbsp@49026000ti,omap3-mcbspyI`mpu 67 commontxrx)mcbsp4txrx}fck disabledmcbsp@48096000ti,omap3-mcbspyH `mpu QR commontxrx)mcbsp5txrx}fck disabledsham@480c3000ti,omap3-shamshamyH 0d1Erxsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_coreyH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivayH timer@48318000ti,omap3430-timeryH1%timer18timer@49032000ti,omap3430-timeryI &timer2timer@49034000ti,omap3430-timeryI@'timer3timer@49036000ti,omap3430-timeryI`(timer4timer@49038000ti,omap3430-timeryI)timer5Gtimer@4903a000ti,omap3430-timeryI*timer6Gtimer@4903c000ti,omap3430-timeryI+timer7Gtimer@4903e000ti,omap3430-timeryI,timer8TGtimer@49040000ti,omap3430-timeryI-timer9Ttimer@48086000ti,omap3430-timeryH`.timer10Ttimer@48088000ti,omap3430-timeryH/timer11Ttimer@48304000ti,omap3430-timeryH0@_timer128ausbhstll@48062000 ti,usbhs-tllyH N usb_tll_hsusbhshost@48064000ti,usbhs-hostyH@ usb_host_hs+ohci@48064400ti,ohci-omap3yHD Lehci@48064800 ti,ehci-omapyHH Mgpmc@6e000000ti,omap3430-gpmcgpmcynrxtxq}+ 08>ethernet@gpmcsmsc,lan9221smsc,lan9115!4(G-Ud-rxKK,DVft  ynand@0,0ti,omap2-nand y  micron,nandbch8,,!"4,r(U6@RRD(,+partition@0 X-Loaderypartition@80000U-Bootypartition@1c0000 Environmentypartition@200000Kernely partition@2000000 Filesystemyusb_otg_hs@480ab000ti,omap3-musbyH \]mcdma usb_otg_hs  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compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-masklinux,phandlepinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0ti,use_poweroffbci3v1-supplyregulator-always-onusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyvcc-supplyti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,swap-xywakeup-sourcependown-gpioti,dual-voltpbias-supplyvmmc-supplybus-widthstatus#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-securegpmc,num-csgpmc,num-waitpinsbank-widthgpmc,device-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addresslinux,mtd-namenand-bus-widthti,nand-ecc-optgpmc,sync-clk-pslabelmultipointnum-epsram-bitsinterface-typeusb-phypowerremote-endpointdata-linesiommusti,phy-type#thermal-sensor-cellsgpioslinux,codedefault-onstartup-delay-uspower-supplyenable-gpiosreset-gpiosmode-gpios