s8p( 8Qincostartec,omap3-lilly-dbb056incostartec,omap3-lilly-a83xti,omap36xxti,omap3 +"7INCOstartec LILLY-DBB056 (DM3730)aliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000d/ocp@68000000/serial@49042000cpus+cpu@0arm,cortex-a8lcpux|cpus 'O 57pmu@54000000arm,cortex-a8-pmuxTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busxh +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busx + pinmux@30 ti,omap3-padconfpinctrl-singlex08++default9pinmux_uart1_pins CLNPRW]pinmux_uart2_pinsC@BW]pinmux_uart3_pinsCnpW]pinmux_i2c1_pinsCW]pinmux_i2c2_pinsCW]pinmux_i2c3_pinsCW]pinmux_hsusb1_pinsCW]pinmux_hsusb_otg_pins`Crtvxz|~W ] pinmux_mmc1_pins0CW]pinmux_spi2_pins CW]pinmux_twl4030_pinsCAW]pinmux_lan9117_pinsCW ] pinmux_gpio4_pinsCW]pinmux_gpio5_pinsC\W]pinmux_lcd_pinsCW]pinmux_mmc2_pins`C(*,.02468:jlW]pinmux_spi1_pins CW]scm_conf@270sysconsimple-busxp0+ p0W]pbias_regulator@2b0ti,pbias-omap3ti,pbias-omapxepbias_mmc_omap2430lpbias_mmc_omap2430{w@-W]clocks+mcbsp5_mux_fck@68ti,composite-mux-clock|xhW]mcbsp5_fckti,composite-clock|W]mcbsp1_mux_fck@4ti,composite-mux-clock|xW ] mcbsp1_fckti,composite-clock| W]mcbsp2_mux_fck@4ti,composite-mux-clock| xW ] mcbsp2_fckti,composite-clock| W]mcbsp3_mux_fck@68ti,composite-mux-clock| xhW]mcbsp3_fckti,composite-clock|W]mcbsp4_mux_fck@68ti,composite-mux-clock| xhW]mcbsp4_fckti,composite-clock|W]clockdomainspinmux@a00 ti,omap3-padconfpinctrl-singlex \++defaultpinmux_lan9221_pinsCZW]pinmux_tsc2048_pinsCW]pinmux_mmc1cd_pinsCVW]pinmux_twl4030_vpins CW]aes@480c5000 ti,omap3-aesaesxH PPABtxrxprm@48306000 ti,omap3-prmxH0`@ clocks+virt_16_8m_ck fixed-clockYW]osc_sys_ck@d40 ti,mux-clock|x @W]sys_ck@1270ti,divider-clock|xpW]sys_clkout1@d70ti,gate-clock|x pdpll3_x2_ckfixed-factor-clock|dpll3_m2x2_ckfixed-factor-clock|W]dpll4_x2_ckfixed-factor-clock|corex2_fckfixed-factor-clock|W]wkup_l4_ickfixed-factor-clock|WN]Ncorex2_d3_fckfixed-factor-clock|W]corex2_d5_fckfixed-factor-clock|W]clockdomainscm@48004000 ti,omap3-cmxH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockW@]@virt_12m_ck fixed-clockW]virt_13m_ck fixed-clock]@W]virt_19200000_ck fixed-clock$W]virt_26000000_ck fixed-clockW]virt_38_4m_ck fixed-clockIW]dpll4_ck@d00ti,omap3-dpll-per-j-type-clock|x D 0W]dpll4_m2_ck@d48ti,divider-clock|?x HW ] dpll4_m2x2_mul_ckfixed-factor-clock| W!]!dpll4_m2x2_ck@d00ti,hsdiv-gate-clock|!x W"]"omap_96m_alwon_fckfixed-factor-clock|"W)])dpll3_ck@d00ti,omap3-dpll-core-clock|x @ 0W]dpll3_m3_ck@1140ti,divider-clock|x@W#]#dpll3_m3x2_mul_ckfixed-factor-clock|#W$]$dpll3_m3x2_ck@d00ti,hsdiv-gate-clock|$ x W%]%emu_core_alwon_ckfixed-factor-clock|%Wb]bsys_altclk fixed-clockW.].mcbsp_clks fixed-clockW]dpll3_m2_ck@d40ti,divider-clock|x @W]core_ckfixed-factor-clock|W&]&dpll1_fck@940ti,divider-clock|&x @W']'dpll1_ck@904ti,omap3-dpll-clock|'x  $ @ 4W]dpll1_x2_ckfixed-factor-clock|W(](dpll1_x2m2_ck@944ti,divider-clock|(x DW<]<cm_96m_fckfixed-factor-clock|)W*]*omap_96m_fck@d40 ti,mux-clock|*x @WE]Edpll4_m3_ck@e40ti,divider-clock| x@W+]+dpll4_m3x2_mul_ckfixed-factor-clock|+W,],dpll4_m3x2_ck@d00ti,hsdiv-gate-clock|,x W-]-omap_54m_fck@d40 ti,mux-clock|-.x @W8]8cm_96m_d2_fckfixed-factor-clock|*W/]/omap_48m_fck@d40 ti,mux-clock|/.x @W0]0omap_12m_fckfixed-factor-clock|0WG]Gdpll4_m4_ck@e40ti,divider-clock| x@W1]1dpll4_m4x2_mul_ckti,fixed-factor-clock|11?LW2]2dpll4_m4x2_ck@d00ti,gate-clock|2x LW]dpll4_m5_ck@f40ti,divider-clock|?x@W3]3dpll4_m5x2_mul_ckti,fixed-factor-clock|31?LW4]4dpll4_m5x2_ck@d00ti,hsdiv-gate-clock|4x LWj]jdpll4_m6_ck@1140ti,divider-clock|?x@W5]5dpll4_m6x2_mul_ckfixed-factor-clock|5W6]6dpll4_m6x2_ck@d00ti,hsdiv-gate-clock|6x W7]7emu_per_alwon_ckfixed-factor-clock|7Wc]cclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock|&x pW9]9clkout2_src_mux_ck@d70ti,composite-mux-clock|&*8x pW:]:clkout2_src_ckti,composite-clock|9:W;];sys_clkout2@d70ti,divider-clock|;@x p_mpu_ckfixed-factor-clock|<W=]=arm_fck@924ti,divider-clock|=x $emu_mpu_alwon_ckfixed-factor-clock|=Wd]dl3_ick@a40ti,divider-clock|&x @W>]>l4_ick@a40ti,divider-clock|>x @W?]?rm_ick@c40ti,divider-clock|?x @gpt10_gate_fck@a00ti,composite-gate-clock| x WA]Agpt10_mux_fck@a40ti,composite-mux-clock|@x @WB]Bgpt10_fckti,composite-clock|ABgpt11_gate_fck@a00ti,composite-gate-clock| x WC]Cgpt11_mux_fck@a40ti,composite-mux-clock|@x @WD]Dgpt11_fckti,composite-clock|CDcore_96m_fckfixed-factor-clock|EW]mmchs2_fck@a00ti,wait-gate-clock|x W]mmchs1_fck@a00ti,wait-gate-clock|x W]i2c3_fck@a00ti,wait-gate-clock|x W]i2c2_fck@a00ti,wait-gate-clock|x W]i2c1_fck@a00ti,wait-gate-clock|x W]mcbsp5_gate_fck@a00ti,composite-gate-clock| x W]mcbsp1_gate_fck@a00ti,composite-gate-clock| x W ] core_48m_fckfixed-factor-clock|0WF]Fmcspi4_fck@a00ti,wait-gate-clock|Fx W]mcspi3_fck@a00ti,wait-gate-clock|Fx W]mcspi2_fck@a00ti,wait-gate-clock|Fx W]mcspi1_fck@a00ti,wait-gate-clock|Fx W]uart2_fck@a00ti,wait-gate-clock|Fx W]uart1_fck@a00ti,wait-gate-clock|Fx  W]core_12m_fckfixed-factor-clock|GWH]Hhdq_fck@a00ti,wait-gate-clock|Hx W]core_l3_ickfixed-factor-clock|>WI]Isdrc_ick@a10ti,wait-gate-clock|Ix W]gpmc_fckfixed-factor-clock|Icore_l4_ickfixed-factor-clock|?WJ]Jmmchs2_ick@a10ti,omap3-interface-clock|Jx W]mmchs1_ick@a10ti,omap3-interface-clock|Jx W]hdq_ick@a10ti,omap3-interface-clock|Jx W]mcspi4_ick@a10ti,omap3-interface-clock|Jx W]mcspi3_ick@a10ti,omap3-interface-clock|Jx W]mcspi2_ick@a10ti,omap3-interface-clock|Jx W]mcspi1_ick@a10ti,omap3-interface-clock|Jx W]i2c3_ick@a10ti,omap3-interface-clock|Jx W]i2c2_ick@a10ti,omap3-interface-clock|Jx W]i2c1_ick@a10ti,omap3-interface-clock|Jx W]uart2_ick@a10ti,omap3-interface-clock|Jx W]uart1_ick@a10ti,omap3-interface-clock|Jx  W]gpt11_ick@a10ti,omap3-interface-clock|Jx  W]gpt10_ick@a10ti,omap3-interface-clock|Jx  W]mcbsp5_ick@a10ti,omap3-interface-clock|Jx  W]mcbsp1_ick@a10ti,omap3-interface-clock|Jx  W]omapctrl_ick@a10ti,omap3-interface-clock|Jx W]dss_tv_fck@e00ti,gate-clock|8xW]dss_96m_fck@e00ti,gate-clock|ExW]dss2_alwon_fck@e00ti,gate-clock|xW]dummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock|x WK]Kgpt1_mux_fck@c40ti,composite-mux-clock|@x @WL]Lgpt1_fckti,composite-clock|KLaes2_ick@a10ti,omap3-interface-clock|Jx W]wkup_32k_fckfixed-factor-clock|@WM]Mgpio1_dbck@c00ti,gate-clock|Mx W]sha12_ick@a10ti,omap3-interface-clock|Jx W]wdt2_fck@c00ti,wait-gate-clock|Mx W]wdt2_ick@c10ti,omap3-interface-clock|Nx W]wdt1_ick@c10ti,omap3-interface-clock|Nx W]gpio1_ick@c10ti,omap3-interface-clock|Nx W]omap_32ksync_ick@c10ti,omap3-interface-clock|Nx W]gpt12_ick@c10ti,omap3-interface-clock|Nx W]gpt1_ick@c10ti,omap3-interface-clock|Nx W]per_96m_fckfixed-factor-clock|)W ] per_48m_fckfixed-factor-clock|0WO]Ouart3_fck@1000ti,wait-gate-clock|Ox W]gpt2_gate_fck@1000ti,composite-gate-clock|xWP]Pgpt2_mux_fck@1040ti,composite-mux-clock|@x@WQ]Qgpt2_fckti,composite-clock|PQgpt3_gate_fck@1000ti,composite-gate-clock|xWR]Rgpt3_mux_fck@1040ti,composite-mux-clock|@x@WS]Sgpt3_fckti,composite-clock|RSgpt4_gate_fck@1000ti,composite-gate-clock|xWT]Tgpt4_mux_fck@1040ti,composite-mux-clock|@x@WU]Ugpt4_fckti,composite-clock|TUgpt5_gate_fck@1000ti,composite-gate-clock|xWV]Vgpt5_mux_fck@1040ti,composite-mux-clock|@x@WW]Wgpt5_fckti,composite-clock|VWgpt6_gate_fck@1000ti,composite-gate-clock|xWX]Xgpt6_mux_fck@1040ti,composite-mux-clock|@x@WY]Ygpt6_fckti,composite-clock|XYgpt7_gate_fck@1000ti,composite-gate-clock|xWZ]Zgpt7_mux_fck@1040ti,composite-mux-clock|@x@W[][gpt7_fckti,composite-clock|Z[gpt8_gate_fck@1000ti,composite-gate-clock| xW\]\gpt8_mux_fck@1040ti,composite-mux-clock|@x@W]]]gpt8_fckti,composite-clock|\]gpt9_gate_fck@1000ti,composite-gate-clock| xW^]^gpt9_mux_fck@1040ti,composite-mux-clock|@x@W_]_gpt9_fckti,composite-clock|^_per_32k_alwon_fckfixed-factor-clock|@W`]`gpio6_dbck@1000ti,gate-clock|`xW]gpio5_dbck@1000ti,gate-clock|`xW]gpio4_dbck@1000ti,gate-clock|`xW]gpio3_dbck@1000ti,gate-clock|`xW]gpio2_dbck@1000ti,gate-clock|`x W]wdt3_fck@1000ti,wait-gate-clock|`x W]per_l4_ickfixed-factor-clock|?Wa]agpio6_ick@1010ti,omap3-interface-clock|axW]gpio5_ick@1010ti,omap3-interface-clock|axW]gpio4_ick@1010ti,omap3-interface-clock|axW]gpio3_ick@1010ti,omap3-interface-clock|axW]gpio2_ick@1010ti,omap3-interface-clock|ax W]wdt3_ick@1010ti,omap3-interface-clock|ax W]uart3_ick@1010ti,omap3-interface-clock|ax W]uart4_ick@1010ti,omap3-interface-clock|axW]gpt9_ick@1010ti,omap3-interface-clock|ax W]gpt8_ick@1010ti,omap3-interface-clock|ax W]gpt7_ick@1010ti,omap3-interface-clock|axW]gpt6_ick@1010ti,omap3-interface-clock|axW]gpt5_ick@1010ti,omap3-interface-clock|axW]gpt4_ick@1010ti,omap3-interface-clock|axW]gpt3_ick@1010ti,omap3-interface-clock|axW]gpt2_ick@1010ti,omap3-interface-clock|axW]mcbsp2_ick@1010ti,omap3-interface-clock|axW]mcbsp3_ick@1010ti,omap3-interface-clock|axW]mcbsp4_ick@1010ti,omap3-interface-clock|axW]mcbsp2_gate_fck@1000ti,composite-gate-clock|xW ] mcbsp3_gate_fck@1000ti,composite-gate-clock|xW]mcbsp4_gate_fck@1000ti,composite-gate-clock|xW]emu_src_mux_ck@1140 ti,mux-clock|bcdx@We]eemu_src_ckti,clkdm-gate-clock|eWf]fpclk_fck@1140ti,divider-clock|fx@pclkx2_fck@1140ti,divider-clock|fx@atclk_fck@1140ti,divider-clock|fx@traceclk_src_fck@1140 ti,mux-clock|bcdx@Wg]gtraceclk_fck@1140ti,divider-clock|g x@secure_32k_fck fixed-clockWh]hgpt12_fckfixed-factor-clock|hwdt1_fckfixed-factor-clock|hsecurity_l4_ick2fixed-factor-clock|?Wi]iaes1_ick@a14ti,omap3-interface-clock|ix rng_ick@a14ti,omap3-interface-clock|ix sha11_ick@a14ti,omap3-interface-clock|ix des1_ick@a14ti,omap3-interface-clock|ix cam_mclk@f00ti,gate-clock|jxLcam_ick@f10!ti,omap3-no-wait-interface-clock|?xW]csi2_96m_fck@f00ti,gate-clock|xW]security_l3_ickfixed-factor-clock|>Wk]kpka_ick@a14ti,omap3-interface-clock|kx icr_ick@a10ti,omap3-interface-clock|Jx des2_ick@a10ti,omap3-interface-clock|Jx mspro_ick@a10ti,omap3-interface-clock|Jx mailboxes_ick@a10ti,omap3-interface-clock|Jx ssi_l4_ickfixed-factor-clock|?Wr]rsr1_fck@c00ti,wait-gate-clock|x sr2_fck@c00ti,wait-gate-clock|x sr_l4_ickfixed-factor-clock|?dpll2_fck@40ti,divider-clock|&x@Wl]ldpll2_ck@4ti,omap3-dpll-clock|lx$@4uWm]mdpll2_m2_ck@44ti,divider-clock|mxDWn]niva2_ck@0ti,wait-gate-clock|nxW]modem_fck@a00ti,omap3-interface-clock|x W]sad2d_ick@a10ti,omap3-interface-clock|>x W]mad2d_ick@a18ti,omap3-interface-clock|>x W]mspro_fck@a00ti,wait-gate-clock|x ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock|x Wo]ossi_ssr_div_fck_3430es2@a40ti,composite-divider-clock|x @$Wp]pssi_ssr_fck_3430es2ti,composite-clock|opWq]qssi_sst_fck_3430es2fixed-factor-clock|qW ] hsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clock|Ix W]ssi_ick_3430es2@a10ti,omap3-ssi-interface-clock|rx W ] usim_gate_fck@c00ti,composite-gate-clock|E x W}]}sys_d2_ckfixed-factor-clock|Wt]tomap_96m_d2_fckfixed-factor-clock|EWu]uomap_96m_d4_fckfixed-factor-clock|EWv]vomap_96m_d8_fckfixed-factor-clock|EWw]womap_96m_d10_fckfixed-factor-clock|E Wx]xdpll5_m2_d4_ckfixed-factor-clock|sWy]ydpll5_m2_d8_ckfixed-factor-clock|sWz]zdpll5_m2_d16_ckfixed-factor-clock|sW{]{dpll5_m2_d20_ckfixed-factor-clock|sW|]|usim_mux_fck@c40ti,composite-mux-clock(|tuvwxyz{|x @W~]~usim_fckti,composite-clock|}~usim_ick@c10ti,omap3-interface-clock|Nx  W]dpll5_ck@d04ti,omap3-dpll-clock|x  $ L 4uW]dpll5_m2_ck@d50ti,divider-clock|x PWs]ssgx_gate_fck@b00ti,composite-gate-clock|&x W]core_d3_ckfixed-factor-clock|&W]core_d4_ckfixed-factor-clock|&W]core_d6_ckfixed-factor-clock|&W]omap_192m_alwon_fckfixed-factor-clock|"W]core_d2_ckfixed-factor-clock|&W]sgx_mux_fck@b40ti,composite-mux-clock |*x @W]sgx_fckti,composite-clock|sgx_ick@b10ti,wait-gate-clock|>x W]cpefuse_fck@a08ti,gate-clock|x W]ts_fck@a08ti,gate-clock|@x W]usbtll_fck@a08ti,wait-gate-clock|sx W]usbtll_ick@a18ti,omap3-interface-clock|Jx W]mmchs3_ick@a10ti,omap3-interface-clock|Jx W]mmchs3_fck@a00ti,wait-gate-clock|x W]dss1_alwon_fck_3430es2@e00ti,dss-gate-clock|xLW]dss_ick_3430es2@e10ti,omap3-dss-interface-clock|?xW]usbhost_120m_fck@1400ti,gate-clock|sxW]usbhost_48m_fck@1400ti,dss-gate-clock|0xW]usbhost_ick@1410ti,omap3-dss-interface-clock|?xW]uart4_fck@1000ti,wait-gate-clock|OxW]clockdomainscore_l3_clkdmti,clockdomain|dpll3_clkdmti,clockdomain|dpll1_clkdmti,clockdomain|per_clkdmti,clockdomainl|emu_clkdmti,clockdomain|fdpll4_clkdmti,clockdomain|wkup_clkdmti,clockdomain$|dss_clkdmti,clockdomain|core_l4_clkdmti,clockdomain|cam_clkdmti,clockdomain|iva2_clkdmti,clockdomain|dpll2_clkdmti,clockdomain|md2d_clkdmti,clockdomain |dpll5_clkdmti,clockdomain|sgx_clkdmti,clockdomain|usbhost_clkdmti,clockdomain |counter@48320000ti,omap-counter32kxH2  counter_32kinterrupt-controller@48200000ti,omap3-intcxH W]dma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaxH`  `W]gpio@48310000ti,omap3-gpioxH1gpio1+default9W]gpio@49050000ti,omap3-gpioxIgpio2gpio@49052000ti,omap3-gpioxI gpio3gpio@49054000ti,omap3-gpioxI@ gpio4+default9W]gpio@49056000ti,omap3-gpioxI`!gpio5+default9W]gpio@49058000ti,omap3-gpioxI"gpio6+default9W]serial@4806a000ti,omap3-uartxH H12txrxuart1l+default9serial@4806c000ti,omap3-uartxHI34txrxuart2l+default9serial@49020000ti,omap3-uartxIJ56txrxuart3l+default9i2c@48070000 ti,omap3-i2cxH8txrx+i2c1'@+default9twl@48xH  ti,twl4030+default9audioti,twl4030-audiocodecrtcti,twl4030-rtc bciti,twl4030-bci watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2{**$regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1{ ' $regulator-vdacti,twl4030-vdac{w@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1{:0$W]regulator-vmmc2ti,twl4030-vmmc2{:0regulator-vusb1v5ti,twl4030-vusb1v5W]regulator-vusb1v8ti,twl4030-vusb1v8W]regulator-vusb3v1ti,twl4030-vusb3v1W]regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2{w@w@regulator-vsimti,twl4030-vsim{w@-gpioti,twl4030-gpiotwl4030-usbti,twl4030-usb 8FTbkW ] pwmti,twl4030-pwmvpwmledti,twl4030-pwmledvpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadmadcti,twl4030-madcregulator-vdd2$i2c@48072000 ti,omap3-i2cxH 9txrx+i2c2'@+default9i2c@48060000 ti,omap3-i2cxH=txrx+i2c3'@+default9gpio@20 mcp,mcp23017x mailbox@48094000ti,omap3-mailboxmailboxxH @dsp  spi@48098000ti,omap2-mcspixH A+mcspi1@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3 okay+default9spi@4809a000ti,omap2-mcspixH B+mcspi2 +,-.tx0rx0tx1rx1 okay+default9tsc2046@0x ti,tsc2046 B@ #0+default9;,D MXV_Pospi@480b8000ti,omap2-mcspixH [+mcspi3 tx0rx0tx1rx1spi@480ba000ti,omap2-mcspixH 0+mcspi4FGtx0rx01w@480b2000 ti,omap3-1wxH :hdq1wmmc@4809c000ti,omap3-hsmmcxH Smmc1=>txrx +default9mmc@480b4000ti,omap3-hsmmcxH @Vmmc2/0txrx okay   +default9mmc@480ad000ti,omap3-hsmmcxH ^mmc3MNtxrx  disabledmmu@480bd400ti,omap2-iommuxH mmu_isp#W]mmu@5d000000ti,omap2-iommux]mmu_iva  disabledwdt@48314000 ti,omap3-wdtxH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspxH@3mpu ;< =commontxrxMmcbsp1 txrx|fck  disabledmcbsp@49022000ti,omap3-mcbspxI I 3mpusidetone>?=commontxrxsidetoneMmcbsp2mcbsp2_sidetone!"txrx|fckick okayW]mcbsp@49024000ti,omap3-mcbspxI@I 3mpusidetoneYZ=commontxrxsidetoneMmcbsp3mcbsp3_sidetonetxrx|fckick  disabledmcbsp@49026000ti,omap3-mcbspxI`3mpu 67 =commontxrxMmcbsp4txrx|fck  disabledmcbsp@48096000ti,omap3-mcbspxH `3mpu QR =commontxrxMmcbsp5txrx|fck  disabledsham@480c3000ti,omap3-shamshamxH 0d1Erxsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_corexH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivaxH timer@48318000ti,omap3430-timerxH1%timer1\timer@49032000ti,omap3430-timerxI &timer2timer@49034000ti,omap3430-timerxI@'timer3timer@49036000ti,omap3430-timerxI`(timer4timer@49038000ti,omap3430-timerxI)timer5ktimer@4903a000ti,omap3430-timerxI*timer6ktimer@4903c000ti,omap3430-timerxI+timer7ktimer@4903e000ti,omap3430-timerxI,timer8xktimer@49040000ti,omap3430-timerxI-timer9xtimer@48086000ti,omap3430-timerxH`.timer10xtimer@48088000ti,omap3430-timerxH/timer11xtimer@48304000ti,omap3430-timerxH0@_timer12\usbhstll@48062000 ti,usbhs-tllxH N usb_tll_hsusbhshost@48064000ti,usbhs-hostxH@ usb_host_hs++default9 ehci-phyohci@48064400ti,ohci-omap3xHD Lehci@48064800 ti,ehci-omapxHH Mgpmc@6e000000ti,omap3430-gpmcgpmcxnrxtx+00 W]nand@0,0ti,omap2-nand x bch86HVdhdzddKKdd <4Ke2K+partition@0MLOxpartition@0x80000u-bootxpartition@0x260000u-boot-environmentx&partition@0x280000kernelx(Ppartition@0x780000 filesystemxxethernet@7,0smsc,lan9221smsc,lan9115H V<h<z   < <dd 24eKKK  x+default9miiethernet@4,0smsc,lan9117smsc,lan9115H VAhAz   A Add <4eKKK  x+default9 miiusb_otg_hs@480ab000ti,omap3-musbxH \]=mcdma usb_otg_hs +3 +default9 <K   Susb2-phyf]2dss@48050000 ti,omap3-dssxH  disabled dss_core|fck+dispc@48050400ti,omap3-dispcxH dss_dispc|fckencoder@4804fc00 ti,omap3-dsixHH@H 3protophypll  disabled dss_dsi1| fcksys_clkencoder@48050800ti,omap3-rfbixH  disabled dss_rfbi|fckickencoder@48050c00ti,omap3-vencxH   disabled dss_venc|fcktv_dac_clkssi-controller@48058000 ti,omap3-ssissi okxHH3sysgddG=gdd_mpu+ |q   ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portxHH3txrx CDssi-port@4805b000ti,omap3-ssi-portxHH3txrx EFserial@49042000ti,omap3-uartxI PQRtxrxuart4l  disabledregulator-abb-mpu ti,abb-v1 labb_mpu_iva+xH0rH0h3base-addressint-addressc||`sO7pinmux@480025a0 ti,omap3-padconfpinctrl-singlexH%\++defaultpinmux_hsusb1_2_pins`C8:<>@BDFHJLNW]pinmux_gpio1_pinsCZ W]isp@480bc000 ti,omap3-ispxH H eports+bandgap@48002524xH%$ti,omap36xx-bandgapchosenAconsole=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0memory@80000000lmemoryxleds gpio-ledsled1lilly-a83x::led1  default-onsoundti,omap-twl4030 lilly-a83xvcc3regulator-fixedlVCC3{2Z2Z$W]hsusb1_phyusb-nop-xceiv0W] compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyoperating-pointsinterruptsti,hwmodsranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinslinux,phandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyregulator-always-onusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csstatusspi-max-frequencypendown-gpiovcc-supplyti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,swap-xywakeup-sourceti,dual-voltpbias-supplycd-gpioscd-invertedvmmc-supplybus-widthcap-sdio-irqcap-sd-highspeedcap-mmc-highspeedwp-gpios#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-securenum-portsport1-modephysgpmc,num-csgpmc,num-waitpinsnand-bus-widthti,nand-ecc-optgpmc,mux-add-datagpmc,device-widthgpmc,wait-pingpmc,wait-monitoring-nsgpmc,burst-lengthgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-samecsengpmc,cycle2cycle-delay-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nslabelbank-widthgpmc,cycle2cycle-diffcsenvddvario-supplyvdd33a-supplyreg-io-widthphy-modesmsc,force-internal-phymultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-type#thermal-sensor-cellsbootargslinux,default-triggerti,modelti,mcbsp