8x( @$nokia,omap3-n9ti,omap36xxti,omap3 + 7Nokia N9aliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000d/ocp@68000000/serial@49042000cpus+cpu@0arm,cortex-a8lcpux|cpu s 'O 57B@pmu@54000000arm,cortex-a8-pmuxTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busxh +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busx + pinmux@30 ti,omap3-padconfpinctrl-singlex08+pinmux_accelerator_pins7KQpinmux_debug_led_pins7KQpinmux_mmc2_pins07(*,.02KQpinmux_wlan_pins7LZpinmux_ssi_pins@7LNPRTVXZKQpinmux_ssi_pins_idle@7LNPRTVXZKQpinmux_modem_core1_pins7JKQscm_conf@270sysconsimple-busxp0+ p0KQpbias_regulator@2b0ti,pbias-omap3ti,pbias-omapxYpbias_mmc_omap2430`pbias_mmc_omap2430ow@-KQclocks+mcbsp5_mux_fck@68ti,composite-mux-clock|xhKQmcbsp5_fckti,composite-clock|KQmcbsp1_mux_fck@4ti,composite-mux-clock|xK Q mcbsp1_fckti,composite-clock| KQmcbsp2_mux_fck@4ti,composite-mux-clock| xK Q mcbsp2_fckti,composite-clock| KQmcbsp3_mux_fck@68ti,composite-mux-clock| xhKQmcbsp3_fckti,composite-clock|KQmcbsp4_mux_fck@68ti,composite-mux-clock| xhKQmcbsp4_fckti,composite-clock|KQclockdomainspinmux@a00 ti,omap3-padconfpinctrl-singlex \+aes@480c5000 ti,omap3-aesaesxH PPABtxrxprm@48306000 ti,omap3-prmxH0`@ clocks+virt_16_8m_ck fixed-clockYKQosc_sys_ck@d40 ti,mux-clock|x @KQsys_ck@1270ti,divider-clock|xpKQsys_clkout1@d70ti,gate-clock|x pdpll3_x2_ckfixed-factor-clock|dpll3_m2x2_ckfixed-factor-clock|KQdpll4_x2_ckfixed-factor-clock|corex2_fckfixed-factor-clock|KQwkup_l4_ickfixed-factor-clock|KNQNcorex2_d3_fckfixed-factor-clock|KQcorex2_d5_fckfixed-factor-clock|KQclockdomainscm@48004000 ti,omap3-cmxH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockK@Q@virt_12m_ck fixed-clockKQvirt_13m_ck fixed-clock]@KQvirt_19200000_ck fixed-clock$KQvirt_26000000_ck fixed-clockKQvirt_38_4m_ck fixed-clockIKQdpll4_ck@d00ti,omap3-dpll-per-j-type-clock|x D 0KQdpll4_m2_ck@d48ti,divider-clock|?x HK Q dpll4_m2x2_mul_ckfixed-factor-clock| K!Q!dpll4_m2x2_ck@d00ti,hsdiv-gate-clock|!x K"Q"omap_96m_alwon_fckfixed-factor-clock|"K)Q)dpll3_ck@d00ti,omap3-dpll-core-clock|x @ 0KQdpll3_m3_ck@1140ti,divider-clock|x@K#Q#dpll3_m3x2_mul_ckfixed-factor-clock|#K$Q$dpll3_m3x2_ck@d00ti,hsdiv-gate-clock|$ x K%Q%emu_core_alwon_ckfixed-factor-clock|%KbQbsys_altclk fixed-clockK.Q.mcbsp_clks fixed-clockKQdpll3_m2_ck@d40ti,divider-clock|x @KQcore_ckfixed-factor-clock|K&Q&dpll1_fck@940ti,divider-clock|&x @K'Q'dpll1_ck@904ti,omap3-dpll-clock|'x  $ @ 4KQdpll1_x2_ckfixed-factor-clock|K(Q(dpll1_x2m2_ck@944ti,divider-clock|(x DK<Q<cm_96m_fckfixed-factor-clock|)K*Q*omap_96m_fck@d40 ti,mux-clock|*x @KEQEdpll4_m3_ck@e40ti,divider-clock| x@K+Q+dpll4_m3x2_mul_ckfixed-factor-clock|+K,Q,dpll4_m3x2_ck@d00ti,hsdiv-gate-clock|,x K-Q-omap_54m_fck@d40 ti,mux-clock|-.x @K8Q8cm_96m_d2_fckfixed-factor-clock|*K/Q/omap_48m_fck@d40 ti,mux-clock|/.x @K0Q0omap_12m_fckfixed-factor-clock|0KGQGdpll4_m4_ck@e40ti,divider-clock| x@K1Q1dpll4_m4x2_mul_ckti,fixed-factor-clock|1%3@K2Q2dpll4_m4x2_ck@d00ti,gate-clock|2x @KQdpll4_m5_ck@f40ti,divider-clock|?x@K3Q3dpll4_m5x2_mul_ckti,fixed-factor-clock|3%3@K4Q4dpll4_m5x2_ck@d00ti,hsdiv-gate-clock|4x @KjQjdpll4_m6_ck@1140ti,divider-clock|?x@K5Q5dpll4_m6x2_mul_ckfixed-factor-clock|5K6Q6dpll4_m6x2_ck@d00ti,hsdiv-gate-clock|6x K7Q7emu_per_alwon_ckfixed-factor-clock|7KcQcclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock|&x pK9Q9clkout2_src_mux_ck@d70ti,composite-mux-clock|&*8x pK:Q:clkout2_src_ckti,composite-clock|9:K;Q;sys_clkout2@d70ti,divider-clock|;@x pSmpu_ckfixed-factor-clock|<K=Q=arm_fck@924ti,divider-clock|=x $emu_mpu_alwon_ckfixed-factor-clock|=KdQdl3_ick@a40ti,divider-clock|&x @K>Q>l4_ick@a40ti,divider-clock|>x @K?Q?rm_ick@c40ti,divider-clock|?x @gpt10_gate_fck@a00ti,composite-gate-clock| x KAQAgpt10_mux_fck@a40ti,composite-mux-clock|@x @KBQBgpt10_fckti,composite-clock|ABgpt11_gate_fck@a00ti,composite-gate-clock| x KCQCgpt11_mux_fck@a40ti,composite-mux-clock|@x @KDQDgpt11_fckti,composite-clock|CDcore_96m_fckfixed-factor-clock|EKQmmchs2_fck@a00ti,wait-gate-clock|x KQmmchs1_fck@a00ti,wait-gate-clock|x KQi2c3_fck@a00ti,wait-gate-clock|x KQi2c2_fck@a00ti,wait-gate-clock|x KQi2c1_fck@a00ti,wait-gate-clock|x KQmcbsp5_gate_fck@a00ti,composite-gate-clock| x KQmcbsp1_gate_fck@a00ti,composite-gate-clock| x K Q core_48m_fckfixed-factor-clock|0KFQFmcspi4_fck@a00ti,wait-gate-clock|Fx KQmcspi3_fck@a00ti,wait-gate-clock|Fx KQmcspi2_fck@a00ti,wait-gate-clock|Fx KQmcspi1_fck@a00ti,wait-gate-clock|Fx KQuart2_fck@a00ti,wait-gate-clock|Fx KQuart1_fck@a00ti,wait-gate-clock|Fx  KQcore_12m_fckfixed-factor-clock|GKHQHhdq_fck@a00ti,wait-gate-clock|Hx KQcore_l3_ickfixed-factor-clock|>KIQIsdrc_ick@a10ti,wait-gate-clock|Ix KQgpmc_fckfixed-factor-clock|Icore_l4_ickfixed-factor-clock|?KJQJmmchs2_ick@a10ti,omap3-interface-clock|Jx KQmmchs1_ick@a10ti,omap3-interface-clock|Jx KQhdq_ick@a10ti,omap3-interface-clock|Jx KQmcspi4_ick@a10ti,omap3-interface-clock|Jx KQmcspi3_ick@a10ti,omap3-interface-clock|Jx KQmcspi2_ick@a10ti,omap3-interface-clock|Jx KQmcspi1_ick@a10ti,omap3-interface-clock|Jx KQi2c3_ick@a10ti,omap3-interface-clock|Jx KQi2c2_ick@a10ti,omap3-interface-clock|Jx KQi2c1_ick@a10ti,omap3-interface-clock|Jx KQuart2_ick@a10ti,omap3-interface-clock|Jx KQuart1_ick@a10ti,omap3-interface-clock|Jx  KQgpt11_ick@a10ti,omap3-interface-clock|Jx  KQgpt10_ick@a10ti,omap3-interface-clock|Jx  KQmcbsp5_ick@a10ti,omap3-interface-clock|Jx  KQmcbsp1_ick@a10ti,omap3-interface-clock|Jx  KQomapctrl_ick@a10ti,omap3-interface-clock|Jx KQdss_tv_fck@e00ti,gate-clock|8xKQdss_96m_fck@e00ti,gate-clock|ExKQdss2_alwon_fck@e00ti,gate-clock|xKQdummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock|x KKQKgpt1_mux_fck@c40ti,composite-mux-clock|@x @KLQLgpt1_fckti,composite-clock|KLaes2_ick@a10ti,omap3-interface-clock|Jx KQwkup_32k_fckfixed-factor-clock|@KMQMgpio1_dbck@c00ti,gate-clock|Mx KQsha12_ick@a10ti,omap3-interface-clock|Jx KQwdt2_fck@c00ti,wait-gate-clock|Mx KQwdt2_ick@c10ti,omap3-interface-clock|Nx KQwdt1_ick@c10ti,omap3-interface-clock|Nx KQgpio1_ick@c10ti,omap3-interface-clock|Nx KQomap_32ksync_ick@c10ti,omap3-interface-clock|Nx KQgpt12_ick@c10ti,omap3-interface-clock|Nx KQgpt1_ick@c10ti,omap3-interface-clock|Nx KQper_96m_fckfixed-factor-clock|)K Q per_48m_fckfixed-factor-clock|0KOQOuart3_fck@1000ti,wait-gate-clock|Ox KQgpt2_gate_fck@1000ti,composite-gate-clock|xKPQPgpt2_mux_fck@1040ti,composite-mux-clock|@x@KQQQgpt2_fckti,composite-clock|PQgpt3_gate_fck@1000ti,composite-gate-clock|xKRQRgpt3_mux_fck@1040ti,composite-mux-clock|@x@KSQSgpt3_fckti,composite-clock|RSgpt4_gate_fck@1000ti,composite-gate-clock|xKTQTgpt4_mux_fck@1040ti,composite-mux-clock|@x@KUQUgpt4_fckti,composite-clock|TUgpt5_gate_fck@1000ti,composite-gate-clock|xKVQVgpt5_mux_fck@1040ti,composite-mux-clock|@x@KWQWgpt5_fckti,composite-clock|VWgpt6_gate_fck@1000ti,composite-gate-clock|xKXQXgpt6_mux_fck@1040ti,composite-mux-clock|@x@KYQYgpt6_fckti,composite-clock|XYgpt7_gate_fck@1000ti,composite-gate-clock|xKZQZgpt7_mux_fck@1040ti,composite-mux-clock|@x@K[Q[gpt7_fckti,composite-clock|Z[gpt8_gate_fck@1000ti,composite-gate-clock| xK\Q\gpt8_mux_fck@1040ti,composite-mux-clock|@x@K]Q]gpt8_fckti,composite-clock|\]gpt9_gate_fck@1000ti,composite-gate-clock| xK^Q^gpt9_mux_fck@1040ti,composite-mux-clock|@x@K_Q_gpt9_fckti,composite-clock|^_per_32k_alwon_fckfixed-factor-clock|@K`Q`gpio6_dbck@1000ti,gate-clock|`xKQgpio5_dbck@1000ti,gate-clock|`xKQgpio4_dbck@1000ti,gate-clock|`xKQgpio3_dbck@1000ti,gate-clock|`xKQgpio2_dbck@1000ti,gate-clock|`x KQwdt3_fck@1000ti,wait-gate-clock|`x KQper_l4_ickfixed-factor-clock|?KaQagpio6_ick@1010ti,omap3-interface-clock|axKQgpio5_ick@1010ti,omap3-interface-clock|axKQgpio4_ick@1010ti,omap3-interface-clock|axKQgpio3_ick@1010ti,omap3-interface-clock|axKQgpio2_ick@1010ti,omap3-interface-clock|ax KQwdt3_ick@1010ti,omap3-interface-clock|ax KQuart3_ick@1010ti,omap3-interface-clock|ax KQuart4_ick@1010ti,omap3-interface-clock|axKQgpt9_ick@1010ti,omap3-interface-clock|ax KQgpt8_ick@1010ti,omap3-interface-clock|ax KQgpt7_ick@1010ti,omap3-interface-clock|axKQgpt6_ick@1010ti,omap3-interface-clock|axKQgpt5_ick@1010ti,omap3-interface-clock|axKQgpt4_ick@1010ti,omap3-interface-clock|axKQgpt3_ick@1010ti,omap3-interface-clock|axKQgpt2_ick@1010ti,omap3-interface-clock|axKQmcbsp2_ick@1010ti,omap3-interface-clock|axKQmcbsp3_ick@1010ti,omap3-interface-clock|axKQmcbsp4_ick@1010ti,omap3-interface-clock|axKQmcbsp2_gate_fck@1000ti,composite-gate-clock|xK Q mcbsp3_gate_fck@1000ti,composite-gate-clock|xKQmcbsp4_gate_fck@1000ti,composite-gate-clock|xKQemu_src_mux_ck@1140 ti,mux-clock|bcdx@KeQeemu_src_ckti,clkdm-gate-clock|eKfQfpclk_fck@1140ti,divider-clock|fx@pclkx2_fck@1140ti,divider-clock|fx@atclk_fck@1140ti,divider-clock|fx@traceclk_src_fck@1140 ti,mux-clock|bcdx@KgQgtraceclk_fck@1140ti,divider-clock|g x@secure_32k_fck fixed-clockKhQhgpt12_fckfixed-factor-clock|hwdt1_fckfixed-factor-clock|hsecurity_l4_ick2fixed-factor-clock|?KiQiaes1_ick@a14ti,omap3-interface-clock|ix rng_ick@a14ti,omap3-interface-clock|ix sha11_ick@a14ti,omap3-interface-clock|ix des1_ick@a14ti,omap3-interface-clock|ix cam_mclk@f00ti,gate-clock|jx@cam_ick@f10!ti,omap3-no-wait-interface-clock|?xKQcsi2_96m_fck@f00ti,gate-clock|xKQsecurity_l3_ickfixed-factor-clock|>KkQkpka_ick@a14ti,omap3-interface-clock|kx icr_ick@a10ti,omap3-interface-clock|Jx des2_ick@a10ti,omap3-interface-clock|Jx mspro_ick@a10ti,omap3-interface-clock|Jx mailboxes_ick@a10ti,omap3-interface-clock|Jx ssi_l4_ickfixed-factor-clock|?KrQrsr1_fck@c00ti,wait-gate-clock|x sr2_fck@c00ti,wait-gate-clock|x sr_l4_ickfixed-factor-clock|?dpll2_fck@40ti,divider-clock|&x@KlQldpll2_ck@4ti,omap3-dpll-clock|lx$@4i{KmQmdpll2_m2_ck@44ti,divider-clock|mxDKnQniva2_ck@0ti,wait-gate-clock|nxKQmodem_fck@a00ti,omap3-interface-clock|x KQsad2d_ick@a10ti,omap3-interface-clock|>x KQmad2d_ick@a18ti,omap3-interface-clock|>x KQmspro_fck@a00ti,wait-gate-clock|x ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock|x KoQossi_ssr_div_fck_3430es2@a40ti,composite-divider-clock|x @$KpQpssi_ssr_fck_3430es2ti,composite-clock|opKqQqssi_sst_fck_3430es2fixed-factor-clock|qKQhsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clock|Ix KQssi_ick_3430es2@a10ti,omap3-ssi-interface-clock|rx KQusim_gate_fck@c00ti,composite-gate-clock|E x K}Q}sys_d2_ckfixed-factor-clock|KtQtomap_96m_d2_fckfixed-factor-clock|EKuQuomap_96m_d4_fckfixed-factor-clock|EKvQvomap_96m_d8_fckfixed-factor-clock|EKwQwomap_96m_d10_fckfixed-factor-clock|E KxQxdpll5_m2_d4_ckfixed-factor-clock|sKyQydpll5_m2_d8_ckfixed-factor-clock|sKzQzdpll5_m2_d16_ckfixed-factor-clock|sK{Q{dpll5_m2_d20_ckfixed-factor-clock|sK|Q|usim_mux_fck@c40ti,composite-mux-clock(|tuvwxyz{|x @K~Q~usim_fckti,composite-clock|}~usim_ick@c10ti,omap3-interface-clock|Nx  KQdpll5_ck@d04ti,omap3-dpll-clock|x  $ L 4i{KQdpll5_m2_ck@d50ti,divider-clock|x PKsQssgx_gate_fck@b00ti,composite-gate-clock|&x KQcore_d3_ckfixed-factor-clock|&KQcore_d4_ckfixed-factor-clock|&KQcore_d6_ckfixed-factor-clock|&KQomap_192m_alwon_fckfixed-factor-clock|"KQcore_d2_ckfixed-factor-clock|&KQsgx_mux_fck@b40ti,composite-mux-clock |*x @KQsgx_fckti,composite-clock|sgx_ick@b10ti,wait-gate-clock|>x KQcpefuse_fck@a08ti,gate-clock|x KQts_fck@a08ti,gate-clock|@x KQusbtll_fck@a08ti,wait-gate-clock|sx KQusbtll_ick@a18ti,omap3-interface-clock|Jx KQmmchs3_ick@a10ti,omap3-interface-clock|Jx KQmmchs3_fck@a00ti,wait-gate-clock|x KQdss1_alwon_fck_3430es2@e00ti,dss-gate-clock|x@KQdss_ick_3430es2@e10ti,omap3-dss-interface-clock|?xKQusbhost_120m_fck@1400ti,gate-clock|sxKQusbhost_48m_fck@1400ti,dss-gate-clock|0xKQusbhost_ick@1410ti,omap3-dss-interface-clock|?xKQuart4_fck@1000ti,wait-gate-clock|OxKQclockdomainscore_l3_clkdmti,clockdomain|dpll3_clkdmti,clockdomain|dpll1_clkdmti,clockdomain|per_clkdmti,clockdomainl|emu_clkdmti,clockdomain|fdpll4_clkdmti,clockdomain|wkup_clkdmti,clockdomain$|dss_clkdmti,clockdomain|core_l4_clkdmti,clockdomain|cam_clkdmti,clockdomain|iva2_clkdmti,clockdomain|dpll2_clkdmti,clockdomain|md2d_clkdmti,clockdomain |dpll5_clkdmti,clockdomain|sgx_clkdmti,clockdomain|usbhost_clkdmti,clockdomain |counter@48320000ti,omap-counter32kxH2  counter_32kinterrupt-controller@48200000ti,omap3-intcxH KQdma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaxH`  `KQgpio@48310000ti,omap3-gpioxH1gpio1KQgpio@49050000ti,omap3-gpioxIgpio2KQgpio@49052000ti,omap3-gpioxI gpio3KQgpio@49054000ti,omap3-gpioxI@ gpio4gpio@49056000ti,omap3-gpioxI`!gpio5KQgpio@49058000ti,omap3-gpioxI"gpio6KQserial@4806a000ti,omap3-uartxH H12txrxuart1lserial@4806c000ti,omap3-uartxHI34txrxuart2lserial@49020000ti,omap3-uartxIJ56txrxuart3li2c@48070000 ti,omap3-i2cxH8txrx+i2c1,@ twl@48xH  ti,twl5031rtcti,twl4030-rtc bciti,twl4030-bci  watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1`vaux1o**KQregulator-vaux2ti,twl4030-vaux2`vaux2ow@w@KQregulator-vaux3ti,twl4030-vaux3`vaux3o**KQregulator-vaux4ti,twl4030-vaux4`vaux4o**regulator-vdd1ti,twl4030-vdd1o ' KQregulator-vdacti,twl4030-vdacow@w@`vdacregulator-vioti,twl4030-vio`vioow@w@KQregulator-vintana1ti,twl4030-vintana1 `vintana1o``regulator-vintana2ti,twl4030-vintana2 `vintana2o)0)0regulator-vintdigti,twl4030-vintdig`vintdigo``regulator-vmmc1ti,twl4030-vmmc1o:0`vmmc1regulator-vmmc2ti,twl4030-vmmc2o--`vmmc2regulator-vusb1v5ti,twl4030-vusb1v5KQregulator-vusb1v8ti,twl4030-vusb1v8KQregulator-vusb3v1ti,twl4030-vusb3v1KQregulator-vpll1ti,twl4030-vpll1`vpll1ow@w@regulator-vpll2ti,twl4030-vpll2ow@w@`vpll2regulator-vsimti,twl4030-vsimow@w@`vsimgpioti,twl4030-gpio#twl4030-usbti,twl4030-usb 0>LZcKQpwmti,twl4030-pwmnpwmledti,twl4030-pwmlednpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadymadcti,twl4030-madcpowerti,twl4030-poweri2c@48072000 ti,omap3-i2cxH 9txrx+i2c2camera@10 nokia,smiax||portendpoint ߍ X0KQi2c@48060000 ti,omap3-i2cxH=txrx+i2c3lis302@1d st,lis3lv02dx*default8BTfx  2,73IYiw..mailbox@48094000ti,omap3-mailboxmailboxxH @/dsp A Lspi@48098000ti,omap2-mcspixH A+mcspi1W@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspixH B+mcspi2W +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspixH [+mcspi3W tx0rx0tx1rx1spi@480ba000ti,omap2-mcspixH 0+mcspi4WFGtx0rx01w@480b2000 ti,omap3-1wxH :hdq1wmmc@4809c000ti,omap3-hsmmcxH Smmc1e=>txrxr disabledmmc@480b4000ti,omap3-hsmmcxH @Vmmc2/0txrx*default8mmc@480ad000ti,omap3-hsmmcxH ^mmc3MNtxrx disabledmmu@480bd400ti,omap2-iommuxH mmu_ispKQmmu@5d000000ti,omap2-iommux]mmu_iva disabledwdt@48314000 ti,omap3-wdtxH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspxH@mpu ;< commontxrxmcbsp1 txrx|fck disabledmcbsp@49022000ti,omap3-mcbspxI I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrx|fckick disabledmcbsp@49024000ti,omap3-mcbspxI@I mpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetonetxrx|fckick disabledmcbsp@49026000ti,omap3-mcbspxI`mpu 67 commontxrxmcbsp4txrx|fck disabledmcbsp@48096000ti,omap3-mcbspxH `mpu QR commontxrxmcbsp5txrx|fck disabledsham@480c3000ti,omap3-shamshamxH 0d1Erxsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_corexH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivaxH timer@48318000ti,omap3430-timerxH1%timer1timer@49032000ti,omap3430-timerxI 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compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinslinux,phandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyti,pullupsti,pulldownsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cellsti,use_poweroffvana-supplynokia,nvm-sizelink-frequenciesclock-lanesdata-lanesremote-endpointVdd-supplyVdd_IO-supplypinctrl-namespinctrl-0st,click-single-xst,click-single-yst,click-single-zst,click-threshold-xst,click-threshold-yst,click-threshold-zst,click-time-limitst,click-latencyst,wakeup-x-hist,wakeup-y-hist,wakeup-thresholdst,wakeup2-z-hist,wakeup2-thresholdst,highpass-cutoff-hzst,irq1-ff-wu-1st,irq1-ff-wu-2st,irq2-clickst,wu-duration-1st,wu-duration-2st,axis-xst,axis-yst,axis-zst,min-limit-xst,min-limit-yst,min-limit-zst,max-limit-xst,max-limit-yst,max-limit-z#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplystatusvmmc-supplybus-widthti,non-removable#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-securegpmc,num-csgpmc,num-waitpinsgpmc,sync-readgpmc,sync-writegpmc,burst-lengthgpmc,burst-readgpmc,burst-wrapgpmc,burst-writegpmc,device-widthgpmc,mux-add-datagpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nsgpmc,sync-clk-pslabelmultipointnum-epsram-bitsinterface-typeusb-phyphysphy-namespowerpinctrl-1ti,ssi-cawake-gpiohsi-channel-idshsi-channel-nameshsi-speed-kbpshsi-modehsi-flowhsi-arb-modegpiosgpio-namesti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-typevdd-csiphy1-supplyvdd-csiphy2-supplycrclane-polarities#thermal-sensor-cellsstartup-delay-usenable-active-highregulator-boot-offlinux,default-trigger