8( pDgumstix,omap3-overo-palo43gumstix,omap3-overoti,omap3430ti,omap3 +!7OMAP35xx Gumstix Overo on Palo43aliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000 d/displaycpus+cpu@0arm,cortex-a8mcpuy}cpu(HАg8 Odp` 'ppmu@54000000arm,cortex-a8-pmuyTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busyh +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busy + pinmux@30 ti,omap3-padconfpinctrl-singley08+,default:DJpinmux_uart2_pins R<>@BDJpinmux_i2c1_pinsRDJpinmux_mmc1_pins0RDJpinmux_mmc2_pins0R(*,.02DJpinmux_w3cbw003c_pinsRlD J pinmux_hsusb2_pins@R      DJpinmux_twl4030_pinsRADJpinmux_i2c3_pinsRDJpinmux_uart3_pinsRnpDJpinmux_dss_dpi_pinsRDJpinmux_lte430_pinsRDDJpinmux_backlight_pinsRFDJpinmux_mcspi1_pins RDJpinmux_ads7846_pinsR DJscm_conf@270sysconsimple-busyp0+ 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pdpll3_x2_ckfixed-factor-clock}dpll3_m2x2_ckfixed-factor-clock}DJdpll4_x2_ckfixed-factor-clock}corex2_fckfixed-factor-clock}DJwkup_l4_ickfixed-factor-clock}DNJNcorex2_d3_fckfixed-factor-clock}DJcorex2_d5_fckfixed-factor-clock}DJclockdomainscm@48004000 ti,omap3-cmyH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockD@J@virt_12m_ck fixed-clockDJvirt_13m_ck fixed-clock]@DJvirt_19200000_ck fixed-clock$DJvirt_26000000_ck fixed-clockDJvirt_38_4m_ck fixed-clockIDJdpll4_ck@d00ti,omap3-dpll-per-clock}y D 0DJdpll4_m2_ck@d48ti,divider-clock}?y HD J dpll4_m2x2_mul_ckfixed-factor-clock} D!J!dpll4_m2x2_ck@d00ti,gate-clock}!y D"J"omap_96m_alwon_fckfixed-factor-clock}"D)J)dpll3_ck@d00ti,omap3-dpll-core-clock}y @ 0DJdpll3_m3_ck@1140ti,divider-clock}y@D#J#dpll3_m3x2_mul_ckfixed-factor-clock}#D$J$dpll3_m3x2_ck@d00ti,gate-clock}$ y D%J%emu_core_alwon_ckfixed-factor-clock}%DbJbsys_altclk fixed-clockD.J.mcbsp_clks fixed-clockDJdpll3_m2_ck@d40ti,divider-clock}y @DJcore_ckfixed-factor-clock}D&J&dpll1_fck@940ti,divider-clock}&y @D'J'dpll1_ck@904ti,omap3-dpll-clock}'y  $ @ 4DJdpll1_x2_ckfixed-factor-clock}D(J(dpll1_x2m2_ck@944ti,divider-clock}(y DD<J<cm_96m_fckfixed-factor-clock})D*J*omap_96m_fck@d40 ti,mux-clock}*y @DEJEdpll4_m3_ck@e40ti,divider-clock} y@D+J+dpll4_m3x2_mul_ckfixed-factor-clock}+D,J,dpll4_m3x2_ck@d00ti,gate-clock},y D-J-omap_54m_fck@d40 ti,mux-clock}-.y @D8J8cm_96m_d2_fckfixed-factor-clock}*D/J/omap_48m_fck@d40 ti,mux-clock}/.y @D0J0omap_12m_fckfixed-factor-clock}0DGJGdpll4_m4_ck@e40ti,divider-clock} y@D1J1dpll4_m4x2_mul_ckti,fixed-factor-clock}12@MD2J2dpll4_m4x2_ck@d00ti,gate-clock}2y MDJdpll4_m5_ck@f40ti,divider-clock}?y@D3J3dpll4_m5x2_mul_ckti,fixed-factor-clock}32@MD4J4dpll4_m5x2_ck@d00ti,gate-clock}4y MDjJjdpll4_m6_ck@1140ti,divider-clock}?y@D5J5dpll4_m6x2_mul_ckfixed-factor-clock}5D6J6dpll4_m6x2_ck@d00ti,gate-clock}6y D7J7emu_per_alwon_ckfixed-factor-clock}7DcJcclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock}&y pD9J9clkout2_src_mux_ck@d70ti,composite-mux-clock}&*8y pD:J:clkout2_src_ckti,composite-clock}9:D;J;sys_clkout2@d70ti,divider-clock};@y p`mpu_ckfixed-factor-clock}<D=J=arm_fck@924ti,divider-clock}=y $emu_mpu_alwon_ckfixed-factor-clock}=DdJdl3_ick@a40ti,divider-clock}&y @D>J>l4_ick@a40ti,divider-clock}>y @D?J?rm_ick@c40ti,divider-clock}?y @gpt10_gate_fck@a00ti,composite-gate-clock} y DAJAgpt10_mux_fck@a40ti,composite-mux-clock}@y @DBJBgpt10_fckti,composite-clock}ABgpt11_gate_fck@a00ti,composite-gate-clock} y DCJCgpt11_mux_fck@a40ti,composite-mux-clock}@y @DDJDgpt11_fckti,composite-clock}CDcore_96m_fckfixed-factor-clock}EDJmmchs2_fck@a00ti,wait-gate-clock}y DJmmchs1_fck@a00ti,wait-gate-clock}y DJi2c3_fck@a00ti,wait-gate-clock}y DJi2c2_fck@a00ti,wait-gate-clock}y DJi2c1_fck@a00ti,wait-gate-clock}y DJmcbsp5_gate_fck@a00ti,composite-gate-clock} y DJmcbsp1_gate_fck@a00ti,composite-gate-clock} y D J core_48m_fckfixed-factor-clock}0DFJFmcspi4_fck@a00ti,wait-gate-clock}Fy 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yD^J^gpt9_mux_fck@1040ti,composite-mux-clock}@y@D_J_gpt9_fckti,composite-clock}^_per_32k_alwon_fckfixed-factor-clock}@D`J`gpio6_dbck@1000ti,gate-clock}`yDJgpio5_dbck@1000ti,gate-clock}`yDJgpio4_dbck@1000ti,gate-clock}`yDJgpio3_dbck@1000ti,gate-clock}`yDJgpio2_dbck@1000ti,gate-clock}`y DJwdt3_fck@1000ti,wait-gate-clock}`y DJper_l4_ickfixed-factor-clock}?DaJagpio6_ick@1010ti,omap3-interface-clock}ayDJgpio5_ick@1010ti,omap3-interface-clock}ayDJgpio4_ick@1010ti,omap3-interface-clock}ayDJgpio3_ick@1010ti,omap3-interface-clock}ayDJgpio2_ick@1010ti,omap3-interface-clock}ay DJwdt3_ick@1010ti,omap3-interface-clock}ay DJuart3_ick@1010ti,omap3-interface-clock}ay DJuart4_ick@1010ti,omap3-interface-clock}ayDJgpt9_ick@1010ti,omap3-interface-clock}ay DJgpt8_ick@1010ti,omap3-interface-clock}ay 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usb_otg_hsDOW `o wusb2-phys2dss@48050000 ti,omap3-dssyHok dss_core}fck+,default:dispc@48050400ti,omap3-dispcyH dss_dispc}fckencoder@4804fc00 ti,omap3-dsiyHH@H }protophypll disabled dss_dsi1} fcksys_clkencoder@48050800ti,omap3-rfbiyH disabled dss_rfbi}fckickencoder@48050c00ti,omap3-vencyH  disabled dss_venc}fckportendpointDJssi-controller@48058000 ti,omap3-ssissiokyHH}sysgddGgdd_mpu+ }q ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portyHH}txrx CDssi-port@4805b000ti,omap3-ssi-portyHH}txrx EFpinmux@480025d8 ti,omap3-padconfpinctrl-singleyH%$+,default:pinmux_hsusb2_2_pins0R   " DJpinmux_w3cbw003c_2_pinsRDJpinmux_led_pinsRDJpinmux_button_pinsRDJisp@480bc000 ti,omap3-ispyH H |flports+bandgap@48002524yH%$ti,omap34xx-bandgapmemory@0mmemoryypwmleds pwm-ledsovero>overo:blue:COM w5mmc0soundti,omap-twl4030overo hsusb2_power_regregulator-fixed mhsusb2_vbus|LK@LK@   p D J hsusb2_phyusb-nop-xceiv + | DJregulator-w3cbw003c-npoweronregulator-fixedmregulator-w3cbw003c-npoweron|2Z2Z   DJregulator-w3cbw003c-wifi-nreset,default: regulator-fixed mregulator-w3cbw003c-wifi-nreset|2Z2Z  'DJregulator-w3cbw003c-bt-nresetregulator-fixedmregulator-w3cbw003c-bt-nreset|2Z2Z   'DJlis33-3v3-regregulator-fixedmlis33-3v3-reg|2Z2ZDJlis33-1v8-regregulator-fixedmlis33-1v8-reg|w@w@DJdisplaysamsung,lte430wq-f0cpanel-dpi>lcd43,default: 7portendpointDJpanel-timinga D L T a m) w      ads7846-regregulator-fixed mads7846-reg|2Z2ZDJbacklightgpio-backlight,default: 1 leds gpio-leds,default:heartbeat>overo:red:gpio21 1 heartbeatgpio22>overo:blue:gpio22 1gpio_keys gpio-keys,default:+button0>button0  1button1>button1  1 compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-pointsinterruptsti,hwmodsranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0linux,phandlepinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyregulator-always-onti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cellsstatuspagesizeVdd-supplyVdd_IO-supplyst,click-single-xst,click-single-yst,click-single-zst,click-thresh-xst,click-thresh-yst,click-thresh-zst,irq1-clickst,irq2-clickst,wakeup-x-lost,wakeup-x-hist,wakeup-y-lost,wakeup-y-hist,wakeup-z-lost,wakeup-z-hist,min-limit-xst,min-limit-yst,min-limit-zst,max-limit-xst,max-limit-yst,max-limit-z#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csvcc-supplyspi-max-frequencypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxwakeup-sourceti,dual-voltpbias-supplyvmmc-supplybus-widthvqmmc-supplyvmmc_aux-supplycap-sdio-irqnon-removable#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport2-modephysgpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerremote-endpointdata-linesiommusti,phy-type#thermal-sensor-cellspwmsmax-brightnesslinux,default-triggerti,modelti,mcbspstartup-delay-usenable-active-highreset-gpiosenable-gpioshactivevactivehfront-porchhback-porchhsync-lenvback-porchvfront-porchvsync-lenhsync-activevsync-activede-activepixelclk-activedefault-onlinux,code