8(Dcompulab,omap3-sbc-t3517compulab,omap3-cm-t3517ti,am3517ti,omap3 +!7CompuLab SBC-T3517 with CM-T3517aliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000d/ocp@68000000/serial@4809e000 l/connector u/connectorcpus+cpu@0arm,cortex-a8~cpucpupmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2iva disableddsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus + pinmux@30 ti,omap3-padconfpinctrl-single08+3defaultApinmux_uart3_pinsKnp_epinmux_mmc1_pins0K_epinmux_green_led_pinsK_epinmux_dss_dpi_pins_commonK_epinmux_dss_dpi_pins_cm_t35x0K_epinmux_ads7846_pinsK_epinmux_mcspi1_pins K_epinmux_i2c1_pinsK_epinmux_mcbsp2_pins K _epinmux_hsusb1_phy_reset_pinsKH_epinmux_hsusb2_phy_reset_pinsKJ_epinmux_otg_drv_vbusK_epinmux_mmc2_pins0K(*,.02_epinmux_wl12xx_core_pinsKF_epinmux_usb_hub_pinsKT_epinmux_smsc2_pinsK_epinmux_tfp410_pinsK_epinmux_i2c3_pinsK_epinmux_sb_t35_audio_ampK_epinmux_mmc1_aux_pinsKD_epinmux_sb_t35_usb_hub_pinsK_escm_conf@270sysconsimple-busp0+ p0_epbias_regulator@2b0ti,pbias-omap3ti,pbias-omapmpbias_mmc_omap2430tpbias_mmc_omap2430w@-_eclocks+mcbsp5_mux_fck@68ti,composite-mux-clockh_ e mcbsp5_fckti,composite-clock _emcbsp1_mux_fck@4ti,composite-mux-clock_ e mcbsp1_fckti,composite-clock _emcbsp2_mux_fck@4ti,composite-mux-clock _emcbsp2_fckti,composite-clock _emcbsp3_mux_fck@68ti,composite-mux-clock h_emcbsp3_fckti,composite-clock_emcbsp4_mux_fck@68ti,composite-mux-clock h_emcbsp4_fckti,composite-clock_eemac_ick@32cti,am35xx-gate-clock,_zezemac_fck@32cti,gate-clock, vpfe_ick@32cti,am35xx-gate-clock,_{e{vpfe_fck@32cti,gate-clock, hsotgusb_ick_am35xx@32cti,am35xx-gate-clock,_|e|hsotgusb_fck_am35xx@32cti,gate-clock,_}e}hecc_ck@32cti,am35xx-gate-clock,_~e~clockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+pinmux_wl12xx_wkup_pinsK_eaes@480c5000 ti,omap3-aesaesH PPABtxrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clockY_eosc_sys_ck@d40 ti,mux-clock @_esys_ck@1270ti,divider-clockp_esys_clkout1@d70ti,gate-clock pdpll3_x2_ckfixed-factor-clockdpll3_m2x2_ckfixed-factor-clock _"e"dpll4_x2_ckfixed-factor-clock!corex2_fckfixed-factor-clock"_#e#wkup_l4_ickfixed-factor-clock_ReRcorex2_d3_fckfixed-factor-clock#_sescorex2_d5_fckfixed-factor-clock#_tetclockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clock_DeDvirt_12m_ck fixed-clock_evirt_13m_ck fixed-clock]@_evirt_19200000_ck fixed-clock$_evirt_26000000_ck fixed-clock_evirt_38_4m_ck fixed-clockI_edpll4_ck@d00ti,omap3-dpll-per-clock D 0_!e!dpll4_m2_ck@d48ti,divider-clock!? H_$e$dpll4_m2x2_mul_ckfixed-factor-clock$_%e%dpll4_m2x2_ck@d00ti,gate-clock% #_&e&omap_96m_alwon_fckfixed-factor-clock&_-e-dpll3_ck@d00ti,omap3-dpll-core-clock @ 0_edpll3_m3_ck@1140ti,divider-clock@_'e'dpll3_m3x2_mul_ckfixed-factor-clock'_(e(dpll3_m3x2_ck@d00ti,gate-clock(  #_)e)emu_core_alwon_ckfixed-factor-clock)_fefsys_altclk fixed-clock_2e2mcbsp_clks fixed-clock_edpll3_m2_ck@d40ti,divider-clock @_ e core_ckfixed-factor-clock _*e*dpll1_fck@940ti,divider-clock* @_+e+dpll1_ck@904ti,omap3-dpll-clock+  $ @ 4_edpll1_x2_ckfixed-factor-clock_,e,dpll1_x2m2_ck@944ti,divider-clock, D_@e@cm_96m_fckfixed-factor-clock-_.e.omap_96m_fck@d40 ti,mux-clock. @_IeIdpll4_m3_ck@e40ti,divider-clock! @_/e/dpll4_m3x2_mul_ckfixed-factor-clock/_0e0dpll4_m3x2_ck@d00ti,gate-clock0 #_1e1omap_54m_fck@d40 ti,mux-clock12 @_<e<cm_96m_d2_fckfixed-factor-clock._3e3omap_48m_fck@d40 ti,mux-clock32 @_4e4omap_12m_fckfixed-factor-clock4_KeKdpll4_m4_ck@e40ti,divider-clock! @_5e5dpll4_m4x2_mul_ckti,fixed-factor-clock59GT_6e6dpll4_m4x2_ck@d00ti,gate-clock6 #T_xexdpll4_m5_ck@f40ti,divider-clock!?@_7e7dpll4_m5x2_mul_ckti,fixed-factor-clock79GT_8e8dpll4_m5x2_ck@d00ti,gate-clock8 #Tdpll4_m6_ck@1140ti,divider-clock!?@_9e9dpll4_m6x2_mul_ckfixed-factor-clock9_:e:dpll4_m6x2_ck@d00ti,gate-clock: #_;e;emu_per_alwon_ckfixed-factor-clock;_gegclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock* p_=e=clkout2_src_mux_ck@d70ti,composite-mux-clock*.< p_>e>clkout2_src_ckti,composite-clock=>_?e?sys_clkout2@d70ti,divider-clock?@ pgmpu_ckfixed-factor-clock@_AeAarm_fck@924ti,divider-clockA $emu_mpu_alwon_ckfixed-factor-clockA_hehl3_ick@a40ti,divider-clock* @_BeBl4_ick@a40ti,divider-clockB @_CeCrm_ick@c40ti,divider-clockC @gpt10_gate_fck@a00ti,composite-gate-clock  _EeEgpt10_mux_fck@a40ti,composite-mux-clockD @_FeFgpt10_fckti,composite-clockEFgpt11_gate_fck@a00ti,composite-gate-clock  _GeGgpt11_mux_fck@a40ti,composite-mux-clockD @_HeHgpt11_fckti,composite-clockGHcore_96m_fckfixed-factor-clockI_emmchs2_fck@a00ti,wait-gate-clock _emmchs1_fck@a00ti,wait-gate-clock _ei2c3_fck@a00ti,wait-gate-clock _ei2c2_fck@a00ti,wait-gate-clock _ei2c1_fck@a00ti,wait-gate-clock _emcbsp5_gate_fck@a00ti,composite-gate-clock  _emcbsp1_gate_fck@a00ti,composite-gate-clock  _ e core_48m_fckfixed-factor-clock4_JeJmcspi4_fck@a00ti,wait-gate-clockJ _emcspi3_fck@a00ti,wait-gate-clockJ _emcspi2_fck@a00ti,wait-gate-clockJ _emcspi1_fck@a00ti,wait-gate-clockJ _euart2_fck@a00ti,wait-gate-clockJ _euart1_fck@a00ti,wait-gate-clockJ  _ecore_12m_fckfixed-factor-clockK_LeLhdq_fck@a00ti,wait-gate-clockL _ecore_l3_ickfixed-factor-clockB_MeMsdrc_ick@a10ti,wait-gate-clockM _yeygpmc_fckfixed-factor-clockMcore_l4_ickfixed-factor-clockC_NeNmmchs2_ick@a10ti,omap3-interface-clockN _emmchs1_ick@a10ti,omap3-interface-clockN _ehdq_ick@a10ti,omap3-interface-clockN _emcspi4_ick@a10ti,omap3-interface-clockN _emcspi3_ick@a10ti,omap3-interface-clockN _emcspi2_ick@a10ti,omap3-interface-clockN _emcspi1_ick@a10ti,omap3-interface-clockN _ei2c3_ick@a10ti,omap3-interface-clockN _ei2c2_ick@a10ti,omap3-interface-clockN _ei2c1_ick@a10ti,omap3-interface-clockN _euart2_ick@a10ti,omap3-interface-clockN _euart1_ick@a10ti,omap3-interface-clockN  _egpt11_ick@a10ti,omap3-interface-clockN  _egpt10_ick@a10ti,omap3-interface-clockN  _emcbsp5_ick@a10ti,omap3-interface-clockN  _emcbsp1_ick@a10ti,omap3-interface-clockN  _eomapctrl_ick@a10ti,omap3-interface-clockN _edss_tv_fck@e00ti,gate-clock<_edss_96m_fck@e00ti,gate-clockI_edss2_alwon_fck@e00ti,gate-clock_edummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock _OeOgpt1_mux_fck@c40ti,composite-mux-clockD @_PePgpt1_fckti,composite-clockOPaes2_ick@a10ti,omap3-interface-clockN _ewkup_32k_fckfixed-factor-clockD_QeQgpio1_dbck@c00ti,gate-clockQ _esha12_ick@a10ti,omap3-interface-clockN _ewdt2_fck@c00ti,wait-gate-clockQ _ewdt2_ick@c10ti,omap3-interface-clockR _ewdt1_ick@c10ti,omap3-interface-clockR _egpio1_ick@c10ti,omap3-interface-clockR _eomap_32ksync_ick@c10ti,omap3-interface-clockR _egpt12_ick@c10ti,omap3-interface-clockR _egpt1_ick@c10ti,omap3-interface-clockR _eper_96m_fckfixed-factor-clock-_ e per_48m_fckfixed-factor-clock4_SeSuart3_fck@1000ti,wait-gate-clockS _egpt2_gate_fck@1000ti,composite-gate-clock_TeTgpt2_mux_fck@1040ti,composite-mux-clockD@_UeUgpt2_fckti,composite-clockTUgpt3_gate_fck@1000ti,composite-gate-clock_VeVgpt3_mux_fck@1040ti,composite-mux-clockD@_WeWgpt3_fckti,composite-clockVWgpt4_gate_fck@1000ti,composite-gate-clock_XeXgpt4_mux_fck@1040ti,composite-mux-clockD@_YeYgpt4_fckti,composite-clockXYgpt5_gate_fck@1000ti,composite-gate-clock_ZeZgpt5_mux_fck@1040ti,composite-mux-clockD@_[e[gpt5_fckti,composite-clockZ[gpt6_gate_fck@1000ti,composite-gate-clock_\e\gpt6_mux_fck@1040ti,composite-mux-clockD@_]e]gpt6_fckti,composite-clock\]gpt7_gate_fck@1000ti,composite-gate-clock_^e^gpt7_mux_fck@1040ti,composite-mux-clockD@__e_gpt7_fckti,composite-clock^_gpt8_gate_fck@1000ti,composite-gate-clock _`e`gpt8_mux_fck@1040ti,composite-mux-clockD@_aeagpt8_fckti,composite-clock`agpt9_gate_fck@1000ti,composite-gate-clock _bebgpt9_mux_fck@1040ti,composite-mux-clockD@_cecgpt9_fckti,composite-clockbcper_32k_alwon_fckfixed-factor-clockD_dedgpio6_dbck@1000ti,gate-clockd_egpio5_dbck@1000ti,gate-clockd_egpio4_dbck@1000ti,gate-clockd_egpio3_dbck@1000ti,gate-clockd_egpio2_dbck@1000ti,gate-clockd _ewdt3_fck@1000ti,wait-gate-clockd _eper_l4_ickfixed-factor-clockC_eeegpio6_ick@1010ti,omap3-interface-clocke_egpio5_ick@1010ti,omap3-interface-clocke_egpio4_ick@1010ti,omap3-interface-clocke_egpio3_ick@1010ti,omap3-interface-clocke_egpio2_ick@1010ti,omap3-interface-clocke _ewdt3_ick@1010ti,omap3-interface-clocke _euart3_ick@1010ti,omap3-interface-clocke _euart4_ick@1010ti,omap3-interface-clocke_egpt9_ick@1010ti,omap3-interface-clocke _egpt8_ick@1010ti,omap3-interface-clocke _egpt7_ick@1010ti,omap3-interface-clocke_egpt6_ick@1010ti,omap3-interface-clocke_egpt5_ick@1010ti,omap3-interface-clocke_egpt4_ick@1010ti,omap3-interface-clocke_egpt3_ick@1010ti,omap3-interface-clocke_egpt2_ick@1010ti,omap3-interface-clocke_emcbsp2_ick@1010ti,omap3-interface-clocke_emcbsp3_ick@1010ti,omap3-interface-clocke_emcbsp4_ick@1010ti,omap3-interface-clocke_emcbsp2_gate_fck@1000ti,composite-gate-clock_ e mcbsp3_gate_fck@1000ti,composite-gate-clock_emcbsp4_gate_fck@1000ti,composite-gate-clock_eemu_src_mux_ck@1140 ti,mux-clockfgh@_ieiemu_src_ckti,clkdm-gate-clocki_jejpclk_fck@1140ti,divider-clockj@pclkx2_fck@1140ti,divider-clockj@atclk_fck@1140ti,divider-clockj@traceclk_src_fck@1140 ti,mux-clockfgh@_kektraceclk_fck@1140ti,divider-clockk @secure_32k_fck fixed-clock_lelgpt12_fckfixed-factor-clocklwdt1_fckfixed-factor-clocklipss_ick@a10ti,am35xx-interface-clockM _ermii_ck fixed-clock_epclk_ck fixed-clock_euart4_ick_am35xx@a10ti,omap3-interface-clockN uart4_fck_am35xx@a00ti,wait-gate-clockJ dpll5_ck@d04ti,omap3-dpll-clock  $ L 4}_memdpll5_m2_ck@d50ti,divider-clockm P_wewsgx_gate_fck@b00ti,composite-gate-clock* _ueucore_d3_ckfixed-factor-clock*_nencore_d4_ckfixed-factor-clock*_oeocore_d6_ckfixed-factor-clock*_pepomap_192m_alwon_fckfixed-factor-clock&_qeqcore_d2_ckfixed-factor-clock*_rersgx_mux_fck@b40ti,composite-mux-clock nop.qrst @_vevsgx_fckti,composite-clockuvsgx_ick@b10ti,wait-gate-clockB _ecpefuse_fck@a08ti,gate-clock _ets_fck@a08ti,gate-clockD _eusbtll_fck@a08ti,wait-gate-clockw _eusbtll_ick@a18ti,omap3-interface-clockN _emmchs3_ick@a10ti,omap3-interface-clockN _emmchs3_fck@a00ti,wait-gate-clock _edss1_alwon_fck_3430es2@e00ti,dss-gate-clockxT_edss_ick_3430es2@e10ti,omap3-dss-interface-clockC_eusbhost_120m_fck@1400ti,gate-clockw_eusbhost_48m_fck@1400ti,dss-gate-clock4_eusbhost_ick@1410ti,omap3-dss-interface-clockC_eclockdomainscore_l3_clkdmti,clockdomainyz{|}~dpll3_clkdmti,clockdomaindpll1_clkdmti,clockdomainper_clkdmti,clockdomainhemu_clkdmti,clockdomainjdpll4_clkdmti,clockdomain!wkup_clkdmti,clockdomain dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaindpll5_clkdmti,clockdomainmsgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain counter@48320000ti,omap-counter32kH2  counter_32kinterrupt-controller@48200000ti,omap3-intcH _edma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaH`  `_egpio@48310000ti,omap3-gpioH1gpio1_egpio@49050000ti,omap3-gpioIgpio2_egpio@49052000ti,omap3-gpioI gpio3_egpio@49054000ti,omap3-gpioI@ gpio4gpio@49056000ti,omap3-gpioI`!gpio5_egpio@49058000ti,omap3-gpioI"gpio6_eserial@4806a000ti,omap3-uartH H12txrxuart1lserial@4806c000ti,omap3-uartHI34txrxuart2lserial@49020000ti,omap3-uartIJ56txrxuart3l3defaultAi2c@48070000 ti,omap3-i2cH8txrx+i2c13defaultAat24@50 at24,24c02Pi2c@48072000 ti,omap3-i2cH 9txrx+i2c2i2c@48060000 ti,omap3-i2cH=txrx+i2c33defaultAat24@50 at24,24c02Pmailbox@48094000ti,omap3-mailboxmailboxH @% disableddsp 7 Bspi@48098000ti,omap2-mcspiH A+mcspi1M@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx33defaultAads7846@03defaultA ti,ads7846[f`  x spi@4809a000ti,omap2-mcspiH B+mcspi2M +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiH [+mcspi3M tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiH 0+mcspi4MFGtx0rx01w@480b2000 ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-hsmmcH Smmc1=>txrx3defaultA!+ 7 @mmc@480b4000ti,omap3-hsmmcH @Vmmc2/0txrx3defaultA+IY!g+wlcore@2 ti,wl1271 zImmc@480ad000ti,omap3-hsmmcH ^mmc3MNtxrx disabledmmu@480bd400ti,omap2-iommuH mmu_isp disabledmmu@5d000000ti,omap2-iommu]mmu_iva disabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspH@mpu ;< commontxrxmcbsp1 txrxfck disabledmcbsp@49022000ti,omap3-mcbspI I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrxfckickok3defaultAmcbsp@49024000ti,omap3-mcbspI@I mpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetonetxrxfckick disabledmcbsp@49026000ti,omap3-mcbspI`mpu 67 commontxrxmcbsp4txrxfck disabledmcbsp@48096000ti,omap3-mcbspH `mpu QR commontxrxmcbsp5txrxfck disabledsham@480c3000ti,omap3-shamshamH 0d1Erxsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_coreH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivaH  disabledtimer@48318000ti,omap3430-timerH1%timer1timer@49032000ti,omap3430-timerI &timer2timer@49034000ti,omap3430-timerI@'timer3timer@49036000ti,omap3430-timerI`(timer4timer@49038000ti,omap3430-timerI)timer5timer@4903a000ti,omap3430-timerI*timer6timer@4903c000ti,omap3430-timerI+timer7timer@4903e000ti,omap3430-timerI,timer8timer@49040000ti,omap3430-timerI-timer9timer@48086000ti,omap3430-timerH`.timer10timer@48088000ti,omap3430-timerH/timer11timer@48304000ti,omap3430-timerH0@_timer12usbhstll@48062000 ti,usbhs-tllH N usb_tll_hsusbhshost@48064000ti,usbhs-hostH@ usb_host_hs+  ehci-phy ehci-phyohci@48064400ti,ohci-omap3HD Lehci@48064800 ti,ehci-omapHH M#gpmc@6e000000ti,omap3430-gpmcgpmcnrxtx(4+ -_enand@0,0ti,omap2-nand  FUgswwxxxxZ Z2HA<[xlx}Z+partition@0xloaderpartition@0x80000ubootpartition@0x260000uboot environment&partition@0x2a0000linux*@partition@0x6a0000rootfsjethernet@4,0smsc,lan9221smsc,lan91153defaultA  Uw(- -[l2xKAK}2BP]usb_otg_hs@480ab000ti,omap3-musbH \]mcdma usb_otg_hss~ dss@48050000 ti,omap3-dssHok dss_corefck+3defaultAdispc@48050400ti,omap3-dispcH dss_dispcfckencoder@4804fc00 ti,omap3-dsiHH@H protophypll disabled dss_dsi1 fcksys_clkencoder@48050800ti,omap3-rfbiH disabled dss_rfbifckickencoder@48050c00ti,omap3-vencH ok dss_vencfckportendpointportendpoint_essi-controller@48058000 ti,omap3-ssissi disabledHHsysgddGgdd_mpu+ssi-port@4805a000ti,omap3-ssi-portHHtxrx CDssi-port@4805b000ti,omap3-ssi-portHHtxrx EFam35x_otg_hs@5c040000ti,omap3-musb am35x_otg_hsokay\Gmc3defaultAethernet@0x5c000000ti,am3517-emac davinci_emacokay\CDEFm $7ethernet@0x5c030000ti,davinci_mdio davinci_mdiookay\IB@+serial@4809e000ti,omap3-uartuart4 disabledH T76txrxlpinmux@480025d8 ti,omap3-padconfpinctrl-singleH%$+memory@80000000~memoryleds gpio-leds3defaultAledb cm-t3x:green : Rheartbeathsusb1_power_regregulator-fixed thsusb1_vbus2Z2Zhp_ehsusb2_power_regregulator-fixed thsusb2_vbus2Z2Zhp_ehsusb1_phyusb-nop-xceiv[3defaultA y_ehsusb2_phyusb-nop-xceiv[3defaultA y_eads7846-regregulator-fixed tads7846-reg2Z2Z_econnectordvi-connectordviportendpoint_eregulator-vmmcregulator-fixedtvmmc2Z2Z_ewl12xx_vmmc2regulator-fixedtvw12713defaultAw@w@ hN _ewl12xx_vaux2regulator-fixedtvwl1271_vaux2w@w@_eencoder ti,tfp410 3defaultAports+port@0endpoint_eport@1endpoint_eaudio_ampregulator-fixed taudio_amp3defaultA regulator-vddvario-sb-t35regulator-fixed tvddvario_eregulator-vdd33a-sb-t35regulator-fixedtvdd33a_e compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2serial3display0display1device_typeregclocksclock-namesclock-latencyinterruptsti,hwmodsstatusranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinslinux,phandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lock#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpagesize#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csvcc-supplyspi-max-frequencypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,debounce-maxti,debounce-tolti,debounce-repwakeup-sourceti,dual-voltpbias-supplybus-widthvmmc-supplywp-gpioscd-gpiosvmmc_aux-supplynon-removablecap-power-off-cardref-clock-frequency#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport1-modeport2-modephysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,page-burst-access-nsgpmc,access-nsgpmc,cycle2cycle-delay-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,bus-turnaround-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsremote-endpointti,channelsdata-linesti,davinci-ctrl-reg-offsetti,davinci-ctrl-mod-reg-offsetti,davinci-ctrl-ram-offsetti,davinci-ctrl-ram-sizeti,davinci-rmii-enlocal-mac-addressbus_freqlinux,default-triggerstartup-delay-usreset-gpiosenable-active-highpowerdown-gpiosenable-active-lowregulator-always-on