M8D( Gtechnexion,omap3-thundertechnexion,omap3-tao3530ti,omap34xxti,omap3 +,7TI OMAP3 Thunder baseboard with TAO3530 SOMaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000 d/displaycpus+cpu@0arm,cortex-a8mcpuy}cpu(HАg8 Odp` 'ppmu@54000000arm,cortex-a8-pmuyTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busyh +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busy + pinmux@30 ti,omap3-padconfpinctrl-singley08+pinmux_hsusbb2_pins`8          pinmux_mmc1_pinsP8 "$&LRpinmux_mmc2_pins08(*,.02LRpinmux_wlan_gpio8^pinmux_uart3_pins8nApLRpinmux_i2c3_pins8LRpinmux_mcspi1_pins 8LRpinmux_mcspi3_pins 8LRpinmux_mcbsp3_pins 8<>@BLRpinmux_twl4030_pins8ALRpinmux_dss_dpi_pins8LRpinmux_lte430_pins88LRpinmux_backlight_pins8:LRscm_conf@270sysconsimple-busyp0+ p0LRpbias_regulator@2b0ti,pbias-omap3ti,pbias-omapyZpbias_mmc_omap2430apbias_mmc_omap2430pw@-LRclocks+mcbsp5_mux_fck@68ti,composite-mux-clock}yhLRmcbsp5_fckti,composite-clock}LRmcbsp1_mux_fck@4ti,composite-mux-clock}yL R mcbsp1_fckti,composite-clock} LRmcbsp2_mux_fck@4ti,composite-mux-clock} yL R mcbsp2_fckti,composite-clock} LRmcbsp3_mux_fck@68ti,composite-mux-clock} yhLRmcbsp3_fckti,composite-clock}LRmcbsp4_mux_fck@68ti,composite-mux-clock} yhLRmcbsp4_fckti,composite-clock}LRclockdomainspinmux@a00 ti,omap3-padconfpinctrl-singley \+pinmux_twl4030_vpins 8LRaes@480c5000 ti,omap3-aesaesyH PPABtxrx disabledprm@48306000 ti,omap3-prmyH0`@ clocks+virt_16_8m_ck fixed-clockYLRosc_sys_ck@d40 ti,mux-clock}y @LRsys_ck@1270ti,divider-clock}ypLRsys_clkout1@d70ti,gate-clock}y pdpll3_x2_ckfixed-factor-clock} dpll3_m2x2_ckfixed-factor-clock} LRdpll4_x2_ckfixed-factor-clock} corex2_fckfixed-factor-clock} LRwkup_l4_ickfixed-factor-clock} LNRNcorex2_d3_fckfixed-factor-clock} LRcorex2_d5_fckfixed-factor-clock} LRclockdomainscm@48004000 ti,omap3-cmyH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockL@R@virt_12m_ck fixed-clockLRvirt_13m_ck fixed-clock]@LRvirt_19200000_ck fixed-clock$LRvirt_26000000_ck fixed-clockLRvirt_38_4m_ck fixed-clockILRdpll4_ck@d00ti,omap3-dpll-per-clock}y D 0LRdpll4_m2_ck@d48ti,divider-clock}?y HL R dpll4_m2x2_mul_ckfixed-factor-clock}  L!R!dpll4_m2x2_ck@d00ti,gate-clock}!y L"R"omap_96m_alwon_fckfixed-factor-clock}" L)R)dpll3_ck@d00ti,omap3-dpll-core-clock}y @ 0LRdpll3_m3_ck@1140ti,divider-clock}y@L#R#dpll3_m3x2_mul_ckfixed-factor-clock}# L$R$dpll3_m3x2_ck@d00ti,gate-clock}$ y L%R%emu_core_alwon_ckfixed-factor-clock}% LbRbsys_altclk fixed-clockL.R.mcbsp_clks fixed-clockLRdpll3_m2_ck@d40ti,divider-clock}y @LRcore_ckfixed-factor-clock} L&R&dpll1_fck@940ti,divider-clock}&y @L'R'dpll1_ck@904ti,omap3-dpll-clock}'y  $ @ 4LRdpll1_x2_ckfixed-factor-clock} L(R(dpll1_x2m2_ck@944ti,divider-clock}(y DL<R<cm_96m_fckfixed-factor-clock}) L*R*omap_96m_fck@d40 ti,mux-clock}*y @LEREdpll4_m3_ck@e40ti,divider-clock} y@L+R+dpll4_m3x2_mul_ckfixed-factor-clock}+ L,R,dpll4_m3x2_ck@d00ti,gate-clock},y L-R-omap_54m_fck@d40 ti,mux-clock}-.y @L8R8cm_96m_d2_fckfixed-factor-clock}* L/R/omap_48m_fck@d40 ti,mux-clock}/.y @L0R0omap_12m_fckfixed-factor-clock}0 LGRGdpll4_m4_ck@e40ti,divider-clock} y@L1R1dpll4_m4x2_mul_ckti,fixed-factor-clock}1-;HL2R2dpll4_m4x2_ck@d00ti,gate-clock}2y HLRdpll4_m5_ck@f40ti,divider-clock}?y@L3R3dpll4_m5x2_mul_ckti,fixed-factor-clock}3-;HL4R4dpll4_m5x2_ck@d00ti,gate-clock}4y HLjRjdpll4_m6_ck@1140ti,divider-clock}?y@L5R5dpll4_m6x2_mul_ckfixed-factor-clock}5 L6R6dpll4_m6x2_ck@d00ti,gate-clock}6y L7R7emu_per_alwon_ckfixed-factor-clock}7 LcRcclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock}&y pL9R9clkout2_src_mux_ck@d70ti,composite-mux-clock}&*8y pL:R:clkout2_src_ckti,composite-clock}9:L;R;sys_clkout2@d70ti,divider-clock};@y p[mpu_ckfixed-factor-clock}< L=R=arm_fck@924ti,divider-clock}=y $emu_mpu_alwon_ckfixed-factor-clock}= LdRdl3_ick@a40ti,divider-clock}&y @L>R>l4_ick@a40ti,divider-clock}>y @L?R?rm_ick@c40ti,divider-clock}?y @gpt10_gate_fck@a00ti,composite-gate-clock} y LARAgpt10_mux_fck@a40ti,composite-mux-clock}@y @LBRBgpt10_fckti,composite-clock}ABgpt11_gate_fck@a00ti,composite-gate-clock} y LCRCgpt11_mux_fck@a40ti,composite-mux-clock}@y @LDRDgpt11_fckti,composite-clock}CDcore_96m_fckfixed-factor-clock}E LRmmchs2_fck@a00ti,wait-gate-clock}y LRmmchs1_fck@a00ti,wait-gate-clock}y LRi2c3_fck@a00ti,wait-gate-clock}y LRi2c2_fck@a00ti,wait-gate-clock}y LRi2c1_fck@a00ti,wait-gate-clock}y LRmcbsp5_gate_fck@a00ti,composite-gate-clock} y LRmcbsp1_gate_fck@a00ti,composite-gate-clock} y L R core_48m_fckfixed-factor-clock}0 LFRFmcspi4_fck@a00ti,wait-gate-clock}Fy LRmcspi3_fck@a00ti,wait-gate-clock}Fy LRmcspi2_fck@a00ti,wait-gate-clock}Fy LRmcspi1_fck@a00ti,wait-gate-clock}Fy LRuart2_fck@a00ti,wait-gate-clock}Fy LRuart1_fck@a00ti,wait-gate-clock}Fy  LRcore_12m_fckfixed-factor-clock}G LHRHhdq_fck@a00ti,wait-gate-clock}Hy LRcore_l3_ickfixed-factor-clock}> LIRIsdrc_ick@a10ti,wait-gate-clock}Iy LRgpmc_fckfixed-factor-clock}I core_l4_ickfixed-factor-clock}? LJRJmmchs2_ick@a10ti,omap3-interface-clock}Jy LRmmchs1_ick@a10ti,omap3-interface-clock}Jy LRhdq_ick@a10ti,omap3-interface-clock}Jy LRmcspi4_ick@a10ti,omap3-interface-clock}Jy LRmcspi3_ick@a10ti,omap3-interface-clock}Jy LRmcspi2_ick@a10ti,omap3-interface-clock}Jy LRmcspi1_ick@a10ti,omap3-interface-clock}Jy LRi2c3_ick@a10ti,omap3-interface-clock}Jy LRi2c2_ick@a10ti,omap3-interface-clock}Jy LRi2c1_ick@a10ti,omap3-interface-clock}Jy LRuart2_ick@a10ti,omap3-interface-clock}Jy LRuart1_ick@a10ti,omap3-interface-clock}Jy  LRgpt11_ick@a10ti,omap3-interface-clock}Jy  LRgpt10_ick@a10ti,omap3-interface-clock}Jy  LRmcbsp5_ick@a10ti,omap3-interface-clock}Jy  LRmcbsp1_ick@a10ti,omap3-interface-clock}Jy  LRomapctrl_ick@a10ti,omap3-interface-clock}Jy LRdss_tv_fck@e00ti,gate-clock}8yLRdss_96m_fck@e00ti,gate-clock}EyLRdss2_alwon_fck@e00ti,gate-clock}yLRdummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock}y LKRKgpt1_mux_fck@c40ti,composite-mux-clock}@y @LLRLgpt1_fckti,composite-clock}KLaes2_ick@a10ti,omap3-interface-clock}Jy LRwkup_32k_fckfixed-factor-clock}@ LMRMgpio1_dbck@c00ti,gate-clock}My LRsha12_ick@a10ti,omap3-interface-clock}Jy LRwdt2_fck@c00ti,wait-gate-clock}My LRwdt2_ick@c10ti,omap3-interface-clock}Ny LRwdt1_ick@c10ti,omap3-interface-clock}Ny LRgpio1_ick@c10ti,omap3-interface-clock}Ny LRomap_32ksync_ick@c10ti,omap3-interface-clock}Ny LRgpt12_ick@c10ti,omap3-interface-clock}Ny LRgpt1_ick@c10ti,omap3-interface-clock}Ny LRper_96m_fckfixed-factor-clock}) L R per_48m_fckfixed-factor-clock}0 LOROuart3_fck@1000ti,wait-gate-clock}Oy LRgpt2_gate_fck@1000ti,composite-gate-clock}yLPRPgpt2_mux_fck@1040ti,composite-mux-clock}@y@LQRQgpt2_fckti,composite-clock}PQgpt3_gate_fck@1000ti,composite-gate-clock}yLRRRgpt3_mux_fck@1040ti,composite-mux-clock}@y@LSRSgpt3_fckti,composite-clock}RSgpt4_gate_fck@1000ti,composite-gate-clock}yLTRTgpt4_mux_fck@1040ti,composite-mux-clock}@y@LURUgpt4_fckti,composite-clock}TUgpt5_gate_fck@1000ti,composite-gate-clock}yLVRVgpt5_mux_fck@1040ti,composite-mux-clock}@y@LWRWgpt5_fckti,composite-clock}VWgpt6_gate_fck@1000ti,composite-gate-clock}yLXRXgpt6_mux_fck@1040ti,composite-mux-clock}@y@LYRYgpt6_fckti,composite-clock}XYgpt7_gate_fck@1000ti,composite-gate-clock}yLZRZgpt7_mux_fck@1040ti,composite-mux-clock}@y@L[R[gpt7_fckti,composite-clock}Z[gpt8_gate_fck@1000ti,composite-gate-clock} yL\R\gpt8_mux_fck@1040ti,composite-mux-clock}@y@L]R]gpt8_fckti,composite-clock}\]gpt9_gate_fck@1000ti,composite-gate-clock} yL^R^gpt9_mux_fck@1040ti,composite-mux-clock}@y@L_R_gpt9_fckti,composite-clock}^_per_32k_alwon_fckfixed-factor-clock}@ L`R`gpio6_dbck@1000ti,gate-clock}`yLRgpio5_dbck@1000ti,gate-clock}`yLRgpio4_dbck@1000ti,gate-clock}`yLRgpio3_dbck@1000ti,gate-clock}`yLRgpio2_dbck@1000ti,gate-clock}`y LRwdt3_fck@1000ti,wait-gate-clock}`y LRper_l4_ickfixed-factor-clock}? LaRagpio6_ick@1010ti,omap3-interface-clock}ayLRgpio5_ick@1010ti,omap3-interface-clock}ayLRgpio4_ick@1010ti,omap3-interface-clock}ayLRgpio3_ick@1010ti,omap3-interface-clock}ayLRgpio2_ick@1010ti,omap3-interface-clock}ay LRwdt3_ick@1010ti,omap3-interface-clock}ay LRuart3_ick@1010ti,omap3-interface-clock}ay LRuart4_ick@1010ti,omap3-interface-clock}ayLRgpt9_ick@1010ti,omap3-interface-clock}ay LRgpt8_ick@1010ti,omap3-interface-clock}ay LRgpt7_ick@1010ti,omap3-interface-clock}ayLRgpt6_ick@1010ti,omap3-interface-clock}ayLRgpt5_ick@1010ti,omap3-interface-clock}ayLRgpt4_ick@1010ti,omap3-interface-clock}ayLRgpt3_ick@1010ti,omap3-interface-clock}ayLRgpt2_ick@1010ti,omap3-interface-clock}ayLRmcbsp2_ick@1010ti,omap3-interface-clock}ayLRmcbsp3_ick@1010ti,omap3-interface-clock}ayLRmcbsp4_ick@1010ti,omap3-interface-clock}ayLRmcbsp2_gate_fck@1000ti,composite-gate-clock}yL R mcbsp3_gate_fck@1000ti,composite-gate-clock}yLRmcbsp4_gate_fck@1000ti,composite-gate-clock}yLRemu_src_mux_ck@1140 ti,mux-clock}bcdy@LeReemu_src_ckti,clkdm-gate-clock}eLfRfpclk_fck@1140ti,divider-clock}fy@pclkx2_fck@1140ti,divider-clock}fy@atclk_fck@1140ti,divider-clock}fy@traceclk_src_fck@1140 ti,mux-clock}bcdy@LgRgtraceclk_fck@1140ti,divider-clock}g y@secure_32k_fck fixed-clockLhRhgpt12_fckfixed-factor-clock}h wdt1_fckfixed-factor-clock}h security_l4_ick2fixed-factor-clock}? LiRiaes1_ick@a14ti,omap3-interface-clock}iy rng_ick@a14ti,omap3-interface-clock}iy sha11_ick@a14ti,omap3-interface-clock}iy des1_ick@a14ti,omap3-interface-clock}iy cam_mclk@f00ti,gate-clock}jyHcam_ick@f10!ti,omap3-no-wait-interface-clock}?yLRcsi2_96m_fck@f00ti,gate-clock}yLRsecurity_l3_ickfixed-factor-clock}> LkRkpka_ick@a14ti,omap3-interface-clock}ky icr_ick@a10ti,omap3-interface-clock}Jy des2_ick@a10ti,omap3-interface-clock}Jy mspro_ick@a10ti,omap3-interface-clock}Jy mailboxes_ick@a10ti,omap3-interface-clock}Jy ssi_l4_ickfixed-factor-clock}? LrRrsr1_fck@c00ti,wait-gate-clock}y sr2_fck@c00ti,wait-gate-clock}y sr_l4_ickfixed-factor-clock}? dpll2_fck@40ti,divider-clock}&y@LlRldpll2_ck@4ti,omap3-dpll-clock}ly$@4qLmRmdpll2_m2_ck@44ti,divider-clock}myDLnRniva2_ck@0ti,wait-gate-clock}nyLRmodem_fck@a00ti,omap3-interface-clock}y LRsad2d_ick@a10ti,omap3-interface-clock}>y LRmad2d_ick@a18ti,omap3-interface-clock}>y LRmspro_fck@a00ti,wait-gate-clock}y ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock}y LoRossi_ssr_div_fck_3430es2@a40ti,composite-divider-clock}y @$LpRpssi_ssr_fck_3430es2ti,composite-clock}opLqRqssi_sst_fck_3430es2fixed-factor-clock}q LRhsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clock}Iy LRssi_ick_3430es2@a10ti,omap3-ssi-interface-clock}ry LRusim_gate_fck@c00ti,composite-gate-clock}E y L}R}sys_d2_ckfixed-factor-clock} LtRtomap_96m_d2_fckfixed-factor-clock}E LuRuomap_96m_d4_fckfixed-factor-clock}E LvRvomap_96m_d8_fckfixed-factor-clock}E LwRwomap_96m_d10_fckfixed-factor-clock}E LxRxdpll5_m2_d4_ckfixed-factor-clock}s LyRydpll5_m2_d8_ckfixed-factor-clock}s LzRzdpll5_m2_d16_ckfixed-factor-clock}s L{R{dpll5_m2_d20_ckfixed-factor-clock}s L|R|usim_mux_fck@c40ti,composite-mux-clock(}tuvwxyz{|y @L~R~usim_fckti,composite-clock}}~usim_ick@c10ti,omap3-interface-clock}Ny  LRdpll5_ck@d04ti,omap3-dpll-clock}y  $ L 4qLRdpll5_m2_ck@d50ti,divider-clock}y PLsRssgx_gate_fck@b00ti,composite-gate-clock}&y LRcore_d3_ckfixed-factor-clock}& LRcore_d4_ckfixed-factor-clock}& LRcore_d6_ckfixed-factor-clock}& LRomap_192m_alwon_fckfixed-factor-clock}" LRcore_d2_ckfixed-factor-clock}& LRsgx_mux_fck@b40ti,composite-mux-clock }*y @LRsgx_fckti,composite-clock}sgx_ick@b10ti,wait-gate-clock}>y LRcpefuse_fck@a08ti,gate-clock}y LRts_fck@a08ti,gate-clock}@y LRusbtll_fck@a08ti,wait-gate-clock}sy LRusbtll_ick@a18ti,omap3-interface-clock}Jy LRmmchs3_ick@a10ti,omap3-interface-clock}Jy LRmmchs3_fck@a00ti,wait-gate-clock}y LRdss1_alwon_fck_3430es2@e00ti,dss-gate-clock}yHLRdss_ick_3430es2@e10ti,omap3-dss-interface-clock}?yLRusbhost_120m_fck@1400ti,gate-clock}syLRusbhost_48m_fck@1400ti,dss-gate-clock}0yLRusbhost_ick@1410ti,omap3-dss-interface-clock}?yLRclockdomainscore_l3_clkdmti,clockdomain}dpll3_clkdmti,clockdomain}dpll1_clkdmti,clockdomain}per_clkdmti,clockdomainh}emu_clkdmti,clockdomain}fdpll4_clkdmti,clockdomain}wkup_clkdmti,clockdomain$}dss_clkdmti,clockdomain}core_l4_clkdmti,clockdomain}cam_clkdmti,clockdomain}iva2_clkdmti,clockdomain}dpll2_clkdmti,clockdomain}md2d_clkdmti,clockdomain }dpll5_clkdmti,clockdomain}sgx_clkdmti,clockdomain}usbhost_clkdmti,clockdomain }counter@48320000ti,omap-counter32kyH2  counter_32kinterrupt-controller@48200000ti,omap3-intcyH LRdma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmayH`  `LRgpio@48310000ti,omap3-gpioyH1gpio1gpio@49050000ti,omap3-gpioyIgpio2gpio@49052000ti,omap3-gpioyI gpio3gpio@49054000ti,omap3-gpioyI@ gpio4gpio@49056000ti,omap3-gpioyI`!gpio5LRgpio@49058000ti,omap3-gpioyI"gpio6LRserial@4806a000ti,omap3-uartyH H12txrxuart1lserial@4806c000ti,omap3-uartyHI34txrxuart2lserial@49020000ti,omap3-uartyIJ56txrxuart3ldefault i2c@48070000 ti,omap3-i2cyH8txrx+i2c1'@twl@48yH  ti,twl4030default audioti,twl4030-audiocodecrtcti,twl4030-rtc bciti,twl4030-bci *watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2 avdd_ehcipw@w@8regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1p ' LRregulator-vdacti,twl4030-vdacpw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1p:0LRregulator-vmmc2ti,twl4030-vmmc2p:0regulator-vusb1v5ti,twl4030-vusb1v5LRregulator-vusb1v8ti,twl4030-vusb1v8LRregulator-vusb3v1ti,twl4030-vusb3v1LRregulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2pw@w@8regulator-vsimti,twl4030-vsimpw@-LRgpioti,twl4030-gpioLXcLRtwl4030-usbti,twl4030-usb p~LRpwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadmadcti,twl4030-madci2c@48072000 ti,omap3-i2cyH 9txrx+i2c2i2c@48060000 ti,omap3-i2cyH=txrx+i2c3default mailbox@48094000ti,omap3-mailboxmailboxyH @ dsp  )spi@48098000ti,omap2-mcspiyH A+mcspi14@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3default spidev@0spidevBlyTspi@4809a000ti,omap2-mcspiyH B+mcspi24 +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiyH [+mcspi34 tx0rx0tx1rx1default spidev@0spidevBlyTspi@480ba000ti,omap2-mcspiyH 0+mcspi44FGtx0rx01w@480b2000 ti,omap3-1wyH :hdq1wmmc@4809c000ti,omap3-hsmmcyH Smmc1]=>txrxjdefault w mmc@480b4000ti,omap3-hsmmcyH @Vmmc2/0txrxdefault wmmc@480ad000ti,omap3-hsmmcyH ^mmc3MNtxrx disabledmmu@480bd400ti,omap2-iommuyH mmu_ispLRmmu@5d000000ti,omap2-iommuy]mmu_iva disabledwdt@48314000 ti,omap3-wdtyH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspyH@mpu ;< commontxrxmcbsp1 txrx}fck disabledmcbsp@49022000ti,omap3-mcbspyI I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrx}fckickokayLRmcbsp@49024000ti,omap3-mcbspyI@I mpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetonetxrx}fckickokaydefault mcbsp@49026000ti,omap3-mcbspyI`mpu 67 commontxrxmcbsp4txrx}fck disabledmcbsp@48096000ti,omap3-mcbspyH `mpu QR commontxrxmcbsp5txrx}fck disabledsham@480c3000ti,omap3-shamshamyH 0d1Erx disabledsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_coreyH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivayH timer@48318000ti,omap3430-timeryH1%timer1 timer@49032000ti,omap3430-timeryI &timer2timer@49034000ti,omap3430-timeryI@'timer3timer@49036000ti,omap3430-timeryI`(timer4timer@49038000ti,omap3430-timeryI)timer5timer@4903a000ti,omap3430-timeryI*timer6timer@4903c000ti,omap3430-timeryI+timer7timer@4903e000ti,omap3430-timeryI,timer8)timer@49040000ti,omap3430-timeryI-timer9)timer@48086000ti,omap3430-timeryH`.timer10)timer@48088000ti,omap3430-timeryH/timer11)timer@48304000ti,omap3430-timeryH0@_timer12 6usbhstll@48062000 ti,usbhs-tllyH N usb_tll_hsusbhshost@48064000ti,usbhs-hostyH@ usb_host_hs+ Fehci-phyohci@48064400ti,ohci-omap3yHD Lehci@48064800 ti,ehci-omapyHH MQgpmc@6e000000ti,omap3430-gpmcgpmcynrxtxVb+0LRnand@0,0ti,omap2-nand y tsw$$$ 0)7FHWHh6w+x-loader@0 X-Loaderybootloaders@80000U-Bootybootloaders_env@260000 U-Boot Envy&kernel@280000Kernely(@filesystem@680000 File Systemyhusb_otg_hs@480ab000ti,omap3-musbyH \]mcdma usb_otg_hs Q usb2-phy2dss@48050000 ti,omap3-dssyHok dss_core}fck+default dispc@48050400ti,omap3-dispcyH dss_dispc}fckencoder@4804fc00 ti,omap3-dsiyHH@H protophypll disabled dss_dsi1} fcksys_clkencoder@48050800ti,omap3-rfbiyH disabled dss_rfbi}fckickencoder@48050c00ti,omap3-vencyH  disabled dss_venc}fckportendpointLRssi-controller@48058000 ti,omap3-ssissiokyHHsysgddGgdd_mpu+ }q ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portyHHtxrx CDssi-port@4805b000ti,omap3-ssi-portyHHtxrx EFpinmux@480025d8 ti,omap3-padconfpinctrl-singleyH%$+isp@480bc000 ti,omap3-ispyH H |Zlports+bandgap@48002524yH%$ti,omap34xx-bandgapmemory@80000000mmemoryyhsusb2_power_regregulator-fixed ahsusb2_vbusp2Z2Z pLRhsusb2_phyusb-nop-xceiv ,8LRsoundti,omap-twl4030 Comap3beagleLregulator-mmc2-sdio-poweronregulator-fixedaregulator-mmc2-sdio-poweronp00 U'LRdisplaysamsung,lte430wq-f0cpanel-dpilcddefault  g portendpointLRpanel-timingT@t|* backlightgpio-backlightdefault    compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinslinux,phandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesstatusclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyregulator-always-onti,use-ledsti,pullupsti,pulldownsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyspi-cphati,dual-voltpbias-supplyvmmc-supplyvmmc_aux-supplycd-gpiosbus-widthnon-removablecap-power-off-card#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport2-modephysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,wr-access-nslabelmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerremote-endpointdata-linesiommusti,phy-type#thermal-sensor-cellsgpiostartup-delay-usreset-gpiosvcc-supplyti,modelti,mcbspenable-active-lowenable-gpioshactivevactivehfront-porchhback-porchhsync-lenvback-porchvfront-porchvsync-lenhsync-activevsync-activede-activepixelclk-activedefault-on