8(ti,omap3430-sdpti,omap3 +7TI OMAP3430 SDPaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000cpus+cpu@0arm,cortex-a8dcpupt{cpu(HАg8 Odp` 'ppmu@54000000arm,cortex-a8-pmupTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busph +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busp + pinmux@30 ti,omap3-padconfpinctrl-singlep08+pinmux_twl4030_pins#A7=scm_conf@270sysconsimple-buspp0+ p07=pbias_regulator@2b0ti,pbias-omap3ti,pbias-omappEpbias_mmc_omap2430Lpbias_mmc_omap2430[w@s-7=clocks+mcbsp5_mux_fck@68ti,composite-mux-clocktph7=mcbsp5_fckti,composite-clockt7=mcbsp1_mux_fck@4ti,composite-mux-clocktp7 = mcbsp1_fckti,composite-clockt 7=mcbsp2_mux_fck@4ti,composite-mux-clockt p7 = mcbsp2_fckti,composite-clockt 7=mcbsp3_mux_fck@68ti,composite-mux-clockt ph7=mcbsp3_fckti,composite-clockt 7=mcbsp4_mux_fck@68ti,composite-mux-clockt ph7=mcbsp4_fckti,composite-clockt7=clockdomainspinmux@a00 ti,omap3-padconfpinctrl-singlep \+pinmux_twl4030_vpins #7=aes@480c5000 ti,omap3-aesaespH PPABtxrxprm@48306000 ti,omap3-prmpH0`@ clocks+virt_16_8m_ck fixed-clockY7=osc_sys_ck@d40 ti,mux-clocktp @7=sys_ck@1270ti,divider-clocktpp7=sys_clkout1@d70ti,gate-clocktp pdpll3_x2_ckfixed-factor-clocktdpll3_m2x2_ckfixed-factor-clockt7=dpll4_x2_ckfixed-factor-clocktcorex2_fckfixed-factor-clockt7=wkup_l4_ickfixed-factor-clockt7M=Mcorex2_d3_fckfixed-factor-clockt7=corex2_d5_fckfixed-factor-clockt7=clockdomainscm@48004000 ti,omap3-cmpH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clock7?=?virt_12m_ck fixed-clock7=virt_13m_ck fixed-clock]@7=virt_19200000_ck fixed-clock$7=virt_26000000_ck fixed-clock7=virt_38_4m_ck fixed-clockI7=dpll4_ck@d00ti,omap3-dpll-per-clocktp D 07=dpll4_m2_ck@d48ti,divider-clockt?p H7=dpll4_m2x2_mul_ckfixed-factor-clockt7 = dpll4_m2x2_ck@d00ti,gate-clockt p 7!=!omap_96m_alwon_fckfixed-factor-clockt!7(=(dpll3_ck@d00ti,omap3-dpll-core-clocktp @ 07=dpll3_m3_ck@1140ti,divider-clocktp@7"="dpll3_m3x2_mul_ckfixed-factor-clockt"7#=#dpll3_m3x2_ck@d00ti,gate-clockt# p 7$=$emu_core_alwon_ckfixed-factor-clockt$7a=asys_altclk fixed-clock7-=-mcbsp_clks fixed-clock7=dpll3_m2_ck@d40ti,divider-clocktp @7=core_ckfixed-factor-clockt7%=%dpll1_fck@940ti,divider-clockt%p @7&=&dpll1_ck@904ti,omap3-dpll-clockt&p  $ @ 47=dpll1_x2_ckfixed-factor-clockt7'='dpll1_x2m2_ck@944ti,divider-clockt'p D7;=;cm_96m_fckfixed-factor-clockt(7)=)omap_96m_fck@d40 ti,mux-clockt)p @7D=Ddpll4_m3_ck@e40ti,divider-clockt p@7*=*dpll4_m3x2_mul_ckfixed-factor-clockt*7+=+dpll4_m3x2_ck@d00ti,gate-clockt+p 7,=,omap_54m_fck@d40 ti,mux-clockt,-p @77=7cm_96m_d2_fckfixed-factor-clockt)7.=.omap_48m_fck@d40 ti,mux-clockt.-p @7/=/omap_12m_fckfixed-factor-clockt/7F=Fdpll4_m4_ck@e40ti,divider-clockt p@70=0dpll4_m4x2_mul_ckti,fixed-factor-clockt0,71=1dpll4_m4x2_ck@d00ti,gate-clockt1p ,7=dpll4_m5_ck@f40ti,divider-clockt?p@72=2dpll4_m5x2_mul_ckti,fixed-factor-clockt2,73=3dpll4_m5x2_ck@d00ti,gate-clockt3p ,7i=idpll4_m6_ck@1140ti,divider-clockt?p@74=4dpll4_m6x2_mul_ckfixed-factor-clockt475=5dpll4_m6x2_ck@d00ti,gate-clockt5p 76=6emu_per_alwon_ckfixed-factor-clockt67b=bclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clockt%p p78=8clkout2_src_mux_ck@d70ti,composite-mux-clockt%)7p p79=9clkout2_src_ckti,composite-clockt897:=:sys_clkout2@d70ti,divider-clockt:@p p?mpu_ckfixed-factor-clockt;7<=<arm_fck@924ti,divider-clockt<p $emu_mpu_alwon_ckfixed-factor-clockt<7c=cl3_ick@a40ti,divider-clockt%p @7===l4_ick@a40ti,divider-clockt=p @7>=>rm_ick@c40ti,divider-clockt>p @gpt10_gate_fck@a00ti,composite-gate-clockt p 7@=@gpt10_mux_fck@a40ti,composite-mux-clockt?p @7A=Agpt10_fckti,composite-clockt@Agpt11_gate_fck@a00ti,composite-gate-clockt p 7B=Bgpt11_mux_fck@a40ti,composite-mux-clockt?p @7C=Cgpt11_fckti,composite-clocktBCcore_96m_fckfixed-factor-clocktD7=mmchs2_fck@a00ti,wait-gate-clocktp 7=mmchs1_fck@a00ti,wait-gate-clocktp 7=i2c3_fck@a00ti,wait-gate-clocktp 7=i2c2_fck@a00ti,wait-gate-clocktp 7=i2c1_fck@a00ti,wait-gate-clocktp 7=mcbsp5_gate_fck@a00ti,composite-gate-clockt p 7=mcbsp1_gate_fck@a00ti,composite-gate-clockt p 7=core_48m_fckfixed-factor-clockt/7E=Emcspi4_fck@a00ti,wait-gate-clocktEp 7=mcspi3_fck@a00ti,wait-gate-clocktEp 7=mcspi2_fck@a00ti,wait-gate-clocktEp 7=mcspi1_fck@a00ti,wait-gate-clocktEp 7=uart2_fck@a00ti,wait-gate-clocktEp 7=uart1_fck@a00ti,wait-gate-clocktEp  7=core_12m_fckfixed-factor-clocktF7G=Ghdq_fck@a00ti,wait-gate-clocktGp 7=core_l3_ickfixed-factor-clockt=7H=Hsdrc_ick@a10ti,wait-gate-clocktHp 7=gpmc_fckfixed-factor-clocktHcore_l4_ickfixed-factor-clockt>7I=Immchs2_ick@a10ti,omap3-interface-clocktIp 7=mmchs1_ick@a10ti,omap3-interface-clocktIp 7=hdq_ick@a10ti,omap3-interface-clocktIp 7=mcspi4_ick@a10ti,omap3-interface-clocktIp 7=mcspi3_ick@a10ti,omap3-interface-clocktIp 7=mcspi2_ick@a10ti,omap3-interface-clocktIp 7=mcspi1_ick@a10ti,omap3-interface-clocktIp 7=i2c3_ick@a10ti,omap3-interface-clocktIp 7=i2c2_ick@a10ti,omap3-interface-clocktIp 7=i2c1_ick@a10ti,omap3-interface-clocktIp 7=uart2_ick@a10ti,omap3-interface-clocktIp 7=uart1_ick@a10ti,omap3-interface-clocktIp  7=gpt11_ick@a10ti,omap3-interface-clocktIp  7=gpt10_ick@a10ti,omap3-interface-clocktIp  7=mcbsp5_ick@a10ti,omap3-interface-clocktIp  7=mcbsp1_ick@a10ti,omap3-interface-clocktIp  7=omapctrl_ick@a10ti,omap3-interface-clocktIp 7=dss_tv_fck@e00ti,gate-clockt7p7=dss_96m_fck@e00ti,gate-clocktDp7=dss2_alwon_fck@e00ti,gate-clocktp7=dummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clocktp 7J=Jgpt1_mux_fck@c40ti,composite-mux-clockt?p @7K=Kgpt1_fckti,composite-clocktJKaes2_ick@a10ti,omap3-interface-clocktIp 7=wkup_32k_fckfixed-factor-clockt?7L=Lgpio1_dbck@c00ti,gate-clocktLp 7=sha12_ick@a10ti,omap3-interface-clocktIp 7=wdt2_fck@c00ti,wait-gate-clocktLp 7=wdt2_ick@c10ti,omap3-interface-clocktMp 7=wdt1_ick@c10ti,omap3-interface-clocktMp 7=gpio1_ick@c10ti,omap3-interface-clocktMp 7=omap_32ksync_ick@c10ti,omap3-interface-clocktMp 7=gpt12_ick@c10ti,omap3-interface-clocktMp 7=gpt1_ick@c10ti,omap3-interface-clocktMp 7=per_96m_fckfixed-factor-clockt(7 = per_48m_fckfixed-factor-clockt/7N=Nuart3_fck@1000ti,wait-gate-clocktNp 7=gpt2_gate_fck@1000ti,composite-gate-clocktp7O=Ogpt2_mux_fck@1040ti,composite-mux-clockt?p@7P=Pgpt2_fckti,composite-clocktOPgpt3_gate_fck@1000ti,composite-gate-clocktp7Q=Qgpt3_mux_fck@1040ti,composite-mux-clockt?p@7R=Rgpt3_fckti,composite-clocktQRgpt4_gate_fck@1000ti,composite-gate-clocktp7S=Sgpt4_mux_fck@1040ti,composite-mux-clockt?p@7T=Tgpt4_fckti,composite-clocktSTgpt5_gate_fck@1000ti,composite-gate-clocktp7U=Ugpt5_mux_fck@1040ti,composite-mux-clockt?p@7V=Vgpt5_fckti,composite-clocktUVgpt6_gate_fck@1000ti,composite-gate-clocktp7W=Wgpt6_mux_fck@1040ti,composite-mux-clockt?p@7X=Xgpt6_fckti,composite-clocktWXgpt7_gate_fck@1000ti,composite-gate-clocktp7Y=Ygpt7_mux_fck@1040ti,composite-mux-clockt?p@7Z=Zgpt7_fckti,composite-clocktYZgpt8_gate_fck@1000ti,composite-gate-clockt p7[=[gpt8_mux_fck@1040ti,composite-mux-clockt?p@7\=\gpt8_fckti,composite-clockt[\gpt9_gate_fck@1000ti,composite-gate-clockt p7]=]gpt9_mux_fck@1040ti,composite-mux-clockt?p@7^=^gpt9_fckti,composite-clockt]^per_32k_alwon_fckfixed-factor-clockt?7_=_gpio6_dbck@1000ti,gate-clockt_p7=gpio5_dbck@1000ti,gate-clockt_p7=gpio4_dbck@1000ti,gate-clockt_p7=gpio3_dbck@1000ti,gate-clockt_p7=gpio2_dbck@1000ti,gate-clockt_p 7=wdt3_fck@1000ti,wait-gate-clockt_p 7=per_l4_ickfixed-factor-clockt>7`=`gpio6_ick@1010ti,omap3-interface-clockt`p7=gpio5_ick@1010ti,omap3-interface-clockt`p7=gpio4_ick@1010ti,omap3-interface-clockt`p7=gpio3_ick@1010ti,omap3-interface-clockt`p7=gpio2_ick@1010ti,omap3-interface-clockt`p 7=wdt3_ick@1010ti,omap3-interface-clockt`p 7=uart3_ick@1010ti,omap3-interface-clockt`p 7=uart4_ick@1010ti,omap3-interface-clockt`p7=gpt9_ick@1010ti,omap3-interface-clockt`p 7=gpt8_ick@1010ti,omap3-interface-clockt`p 7=gpt7_ick@1010ti,omap3-interface-clockt`p7=gpt6_ick@1010ti,omap3-interface-clockt`p7=gpt5_ick@1010ti,omap3-interface-clockt`p7=gpt4_ick@1010ti,omap3-interface-clockt`p7=gpt3_ick@1010ti,omap3-interface-clockt`p7=gpt2_ick@1010ti,omap3-interface-clockt`p7=mcbsp2_ick@1010ti,omap3-interface-clockt`p7=mcbsp3_ick@1010ti,omap3-interface-clockt`p7=mcbsp4_ick@1010ti,omap3-interface-clockt`p7=mcbsp2_gate_fck@1000ti,composite-gate-clocktp7 = mcbsp3_gate_fck@1000ti,composite-gate-clocktp7 = mcbsp4_gate_fck@1000ti,composite-gate-clocktp7=emu_src_mux_ck@1140 ti,mux-clocktabcp@7d=demu_src_ckti,clkdm-gate-clocktd7e=epclk_fck@1140ti,divider-clocktep@pclkx2_fck@1140ti,divider-clocktep@atclk_fck@1140ti,divider-clocktep@traceclk_src_fck@1140 ti,mux-clocktabcp@7f=ftraceclk_fck@1140ti,divider-clocktf p@secure_32k_fck fixed-clock7g=ggpt12_fckfixed-factor-clocktgwdt1_fckfixed-factor-clocktgsecurity_l4_ick2fixed-factor-clockt>7h=haes1_ick@a14ti,omap3-interface-clockthp rng_ick@a14ti,omap3-interface-clockthp sha11_ick@a14ti,omap3-interface-clockthp des1_ick@a14ti,omap3-interface-clockthp cam_mclk@f00ti,gate-clocktip,cam_ick@f10!ti,omap3-no-wait-interface-clockt>p7=csi2_96m_fck@f00ti,gate-clocktp7=security_l3_ickfixed-factor-clockt=7j=jpka_ick@a14ti,omap3-interface-clocktjp icr_ick@a10ti,omap3-interface-clocktIp des2_ick@a10ti,omap3-interface-clocktIp mspro_ick@a10ti,omap3-interface-clocktIp mailboxes_ick@a10ti,omap3-interface-clocktIp ssi_l4_ickfixed-factor-clockt>7q=qsr1_fck@c00ti,wait-gate-clocktp sr2_fck@c00ti,wait-gate-clocktp sr_l4_ickfixed-factor-clockt>dpll2_fck@40ti,divider-clockt%p@7k=kdpll2_ck@4ti,omap3-dpll-clocktkp$@4Ugo7l=ldpll2_m2_ck@44ti,divider-clocktlpD7m=miva2_ck@0ti,wait-gate-clocktmp7=modem_fck@a00ti,omap3-interface-clocktp 7=sad2d_ick@a10ti,omap3-interface-clockt=p 7=mad2d_ick@a18ti,omap3-interface-clockt=p 7=mspro_fck@a00ti,wait-gate-clocktp ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clocktp 7n=nssi_ssr_div_fck_3430es2@a40ti,composite-divider-clocktp @$7o=ossi_ssr_fck_3430es2ti,composite-clocktno7p=pssi_sst_fck_3430es2fixed-factor-clocktp7=hsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clocktHp 7=ssi_ick_3430es2@a10ti,omap3-ssi-interface-clocktqp 7=usim_gate_fck@c00ti,composite-gate-clocktD p 7|=|sys_d2_ckfixed-factor-clockt7s=somap_96m_d2_fckfixed-factor-clocktD7t=tomap_96m_d4_fckfixed-factor-clocktD7u=uomap_96m_d8_fckfixed-factor-clocktD7v=vomap_96m_d10_fckfixed-factor-clocktD 7w=wdpll5_m2_d4_ckfixed-factor-clocktr7x=xdpll5_m2_d8_ckfixed-factor-clocktr7y=ydpll5_m2_d16_ckfixed-factor-clocktr7z=zdpll5_m2_d20_ckfixed-factor-clocktr7{={usim_mux_fck@c40ti,composite-mux-clock(tstuvwxyz{p @7}=}usim_fckti,composite-clockt|}usim_ick@c10ti,omap3-interface-clocktMp  7=dpll5_ck@d04ti,omap3-dpll-clocktp  $ L 4Ug7~=~dpll5_m2_ck@d50ti,divider-clockt~p P7r=rsgx_gate_fck@b00ti,composite-gate-clockt%p 7=core_d3_ckfixed-factor-clockt%7=core_d4_ckfixed-factor-clockt%7=core_d6_ckfixed-factor-clockt%7=omap_192m_alwon_fckfixed-factor-clockt!7=core_d2_ckfixed-factor-clockt%7=sgx_mux_fck@b40ti,composite-mux-clock t)p @7=sgx_fckti,composite-clocktsgx_ick@b10ti,wait-gate-clockt=p 7=cpefuse_fck@a08ti,gate-clocktp 7=ts_fck@a08ti,gate-clockt?p 7=usbtll_fck@a08ti,wait-gate-clocktrp 7=usbtll_ick@a18ti,omap3-interface-clocktIp 7=mmchs3_ick@a10ti,omap3-interface-clocktIp 7=mmchs3_fck@a00ti,wait-gate-clocktp 7=dss1_alwon_fck_3430es2@e00ti,dss-gate-clocktp,7=dss_ick_3430es2@e10ti,omap3-dss-interface-clockt>p7=usbhost_120m_fck@1400ti,gate-clocktrp7=usbhost_48m_fck@1400ti,dss-gate-clockt/p7=usbhost_ick@1410ti,omap3-dss-interface-clockt>p7=clockdomainscore_l3_clkdmti,clockdomaintdpll3_clkdmti,clockdomaintdpll1_clkdmti,clockdomaintper_clkdmti,clockdomainhtemu_clkdmti,clockdomaintedpll4_clkdmti,clockdomaintwkup_clkdmti,clockdomain$tdss_clkdmti,clockdomaintcore_l4_clkdmti,clockdomaintcam_clkdmti,clockdomaintiva2_clkdmti,clockdomaintdpll2_clkdmti,clockdomaintld2d_clkdmti,clockdomain tdpll5_clkdmti,clockdomaint~sgx_clkdmti,clockdomaintusbhost_clkdmti,clockdomain tcounter@48320000ti,omap-counter32kpH2  counter_32kinterrupt-controller@48200000ti,omap3-intcpH 7=dma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmapH`  `7=gpio@48310000ti,omap3-gpiopH1gpio1gpio@49050000ti,omap3-gpiopIgpio2gpio@49052000ti,omap3-gpiopI gpio3gpio@49054000ti,omap3-gpiopI@ gpio4gpio@49056000ti,omap3-gpiopI`!gpio5gpio@49058000ti,omap3-gpiopI"gpio6serial@4806a000ti,omap3-uartpH H12txrxuart1lserial@4806c000ti,omap3-uartpHI34txrxuart2lserial@49020000ti,omap3-uartpIJ56txrxuart3li2c@48070000 ti,omap3-i2cpH8txrx+i2c1'@twl@48pH ti,twl4030defaultrtcti,twl4030-rtc bciti,twl4030-bci watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1[ 's regulator-vdacti,twl4030-vdac[w@sw@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1[:s07=regulator-vmmc2ti,twl4030-vmmc2[:s0regulator-vusb1v5ti,twl4030-vusb1v57=regulator-vusb1v8ti,twl4030-vusb1v87=regulator-vusb3v1ti,twl4030-vusb3v17=regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2[w@sw@regulator-vsimti,twl4030-vsim[w@s-7=gpioti,twl4030-gpiotwl4030-usbti,twl4030-usb *8FOpwmti,twl4030-pwmZpwmledti,twl4030-pwmledZpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadeumadcti,twl4030-madci2c@48072000 ti,omap3-i2cpH 9txrx+i2c2i2c@48060000 ti,omap3-i2cpH=txrx+i2c3mailbox@48094000ti,omap3-mailboxmailboxpH @dsp  spi@48098000ti,omap2-mcspipH A+mcspi1@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspipH B+mcspi2 +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspipH [+mcspi3 tx0rx0tx1rx1spi@480ba000ti,omap2-mcspipH 0+mcspi4FGtx0rx01w@480b2000 ti,omap3-1wpH :hdq1wmmc@4809c000ti,omap3-hsmmcpH Smmc1=>txrx$mmc@480b4000ti,omap3-hsmmcpH @Vmmc2/0txrx .disabledmmc@480ad000ti,omap3-hsmmcpH ^mmc3MNtxrx .disabledmmu@480bd4005ti,omap2-iommupH mmu_ispB7=mmu@5d0000005ti,omap2-iommup]mmu_iva .disabledwdt@48314000 ti,omap3-wdtpH1@ wd_timer2mcbsp@48074000ti,omap3-mcbsppH@Rmpu ;< \commontxrxlmcbsp1 txrxt{fck .disabledmcbsp@49022000ti,omap3-mcbsppI I Rmpusidetone>?\commontxrxsidetonelmcbsp2mcbsp2_sidetone!"txrxt{fckick .disabledmcbsp@49024000ti,omap3-mcbsppI@I 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compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2device_typeregclocksclock-namesclock-latencyoperating-pointsinterruptsti,hwmodsranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinslinux,phandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplyvmmc_aux-supplybus-widthstatus#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-securegpmc,num-csgpmc,num-waitpinslinux,mtd-namebank-widthgpmc,mux-add-datagpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nsgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsenlabelti,nand-ecc-optnand-bus-widthgpmc,device-widthmultipointnum-epsram-bitsiommusti,phy-type#thermal-sensor-cells