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 fdif_fck@1028rti,divider-clockž8œš(ügpio2_dbclk@1460rti,gate-clockž,š`gpio3_dbclk@1468rti,gate-clockž,šhgpio4_dbclk@1470rti,gate-clockž,špgpio5_dbclk@1478rti,gate-clockž,šxgpio6_dbclk@1480rti,gate-clockž,š€sgx_clk_mux@1220r ti,mux-clockž=>š hsi_fck@1338rti,divider-clockž6œš8üiss_ctrlclk@1020rti,gate-clockž?š mcbsp4_sync_mux_ck@14e0r ti,mux-clockž?@šàA Aper_mcbsp4_gfclk@14e0r ti,mux-clockžA&šàhsmmc1_fclk@1328r ti,mux-clockžB?š(hsmmc2_fclk@1330r ti,mux-clockžB?š0ocp2scp_usb_phy_phy_48m@13e0rti,gate-clockžCšàsha2md5_fck@15c8rti,gate-clockžšÈslimbus2_fclk_1@1538rti,gate-clockžD š8slimbus2_fclk_0@1538rti,gate-clockžEš8slimbus2_slimbus_clk@1538rti,gate-clockžF š8smartreflex_core_fck@638rti,gate-clockžGš8smartreflex_iva_fck@630rti,gate-clockžGš0smartreflex_mpu_fck@628rti,gate-clockžGš(cm2_dm10_mux@1428r ti,mux-clockž,š(cm2_dm11_mux@1430r ti,mux-clockž,š0cm2_dm2_mux@1438r ti,mux-clockž,š8cm2_dm3_mux@1440r ti,mux-clockž,š@cm2_dm4_mux@1448r ti,mux-clockž,šHcm2_dm9_mux@1450r ti,mux-clockž,šPusb_host_fs_fck@13d0rti,gate-clockž<šÐQ Qutmi_p1_gfclk@1358r ti,mux-clockžHIšXJ Jusb_host_hs_utmi_p1_clk@1358rti,gate-clockžJšXutmi_p2_gfclk@1358r ti,mux-clockžHKšXL Lusb_host_hs_utmi_p2_clk@1358rti,gate-clockžL šXusb_host_hs_utmi_p3_clk@1358rti,gate-clockžH šXusb_host_hs_hsic480m_p1_clk@1358rti,gate-clockž9 šXusb_host_hs_hsic60m_p1_clk@1358rti,gate-clockžH šXusb_host_hs_hsic60m_p2_clk@1358rti,gate-clockžH šXusb_host_hs_hsic480m_p2_clk@1358rti,gate-clockž9šXusb_host_hs_func48mclk@1358rti,gate-clockž<šXusb_host_hs_fck@1358rti,gate-clockžHšXotg_60m_gfclk@1360r ti,mux-clockžMNš`O Ousb_otg_hs_xclk@1360rti,gate-clockžOš`usb_otg_hs_ick@1360rti,gate-clockžš`usb_phy_cm_clk32k@640rti,gate-clockž,š@˜ ˜usb_tll_hs_usb_ch2_clk@1368rti,gate-clockžH šhusb_tll_hs_usb_ch0_clk@1368rti,gate-clockžHšhusb_tll_hs_usb_ch1_clk@1368rti,gate-clockžH šhusb_tll_hs_ick@1368rti,gate-clockžPšhclockdomainsl3_init_clkdmti,clockdomainž4Qscm@2000ti,omap4-scm-coresimple-busš + k scm_conf@0sysconš+scm@100000%ti,omap4-scm-padconf-coresimple-bus+ kpinmux@40 ti,omap4-padconfpinctrl-singleš@–+&Ljÿ‡default•RSTUV‚ ‚pinmux_twl6040_pinsŸà`‡ ‡pinmux_mcpdm_pins(ŸÆÈÊÌΓ “pinmux_mcbsp1_pins Ÿ¾ÀÂÄ• •pinmux_dss_dpi_pinsàŸ"$&(*,.0246tvxz|~€‚„†ˆŠŒŽ’”R Rpinmux_tfp410_pinsŸDS Spinmux_dss_hdmi_pinsŸZ\^T Tpinmux_tpd12s015_pinsŸ"HX U Upinmux_hsusbb1_pins`Ÿ‚ „† ˆ Š Œ Ž  ’ ” – ˜ V Vpinmux_i2c1_pinsŸâäƒ ƒpinmux_i2c2_pinsŸæè‹ ‹pinmux_i2c3_pinsŸêìŒ Œpinmux_i2c4_pinsŸîð pinmux_wl12xx_gpio Ÿ&,02« «pinmux_wl12xx_pins@Ÿ8:   pinmux_twl6030_pinsŸ^A„ „omap4_padconf_global@5a0sysconsimple-busš p+ k pW Wpbias_regulator@60ti,pbias-omap4ti,pbias-omapš`³Wpbias_mmc_omap4ºpbias_mmc_omap4Éw@á-ÆÀŽ Žl4@300000ti,omap4-l4-wkupsimple-bus+ k0counter@4000ti,omap-counter32kš@  \counter_32kprm@6000 ti,omap4-prmš`0 Q clocks+sys_clkin_ck@110r ti,mux-clockžXYZ[\]^š¹ abe_dpll_bypass_clk_mux_ck@108r ti,mux-clockž,š  abe_dpll_refclk_mux_ck@10cr ti,mux-clockž,š   dbgclk_mux_ckrfixed-factor-clockžçòl4_wkup_clk_mux_ck@108r ti,mux-clockž_šG Gsyc_clk_div_ck@100rti,divider-clockžšœ# #gpio1_dbclk@1838rti,gate-clockž,š8dmt1_clk_mux@1840r ti,mux-clockž,š@usim_ck@1858rti,divider-clockž8šX` `usim_fclk@1858rti,gate-clockž`šXpmd_stm_clock_mux_ck@1a20r ti,mux-clock žabš c cpmd_trace_clk_mux_ck@1a20r ti,mux-clock žabš d dstm_clk_div_ck@1a20rti,divider-clockžcœ@š ütrace_clk_div_div_ck@1a20rti,divider-clockždš e etrace_clk_div_ckrti,clkdm-gate-clockžef fbandgap_fclk@1888rti,gate-clockž,šˆclockdomainsemu_sys_clkdmti,clockdomainžfscrm@a000ti,omap4-scrmš  clocks+auxclk0_src_gate_ck@310r ti,composite-no-wait-gate-clockžgši iauxclk0_src_mux_ck@310rti,composite-mux-clock žghšj jauxclk0_src_ckrti,composite-clockžijk kauxclk0_ck@310rti,divider-clockžkœš{ {auxclk1_src_gate_ck@314r ti,composite-no-wait-gate-clockžgšl lauxclk1_src_mux_ck@314rti,composite-mux-clock žghšm mauxclk1_src_ckrti,composite-clockžlmn nauxclk1_ck@314rti,divider-clockžnœš| |auxclk2_src_gate_ck@318r ti,composite-no-wait-gate-clockžgšo oauxclk2_src_mux_ck@318rti,composite-mux-clock žghšp pauxclk2_src_ckrti,composite-clockžopq qauxclk2_ck@318rti,divider-clockžqœš} }auxclk3_src_gate_ck@31cr ti,composite-no-wait-gate-clockžgšr rauxclk3_src_mux_ck@31crti,composite-mux-clock žghšs sauxclk3_src_ckrti,composite-clockžrst tauxclk3_ck@31crti,divider-clockžtœš~ ~auxclk4_src_gate_ck@320r ti,composite-no-wait-gate-clockžgš u uauxclk4_src_mux_ck@320rti,composite-mux-clock žghš v vauxclk4_src_ckrti,composite-clockžuvw wauxclk4_ck@320rti,divider-clockžwœš  auxclk5_src_gate_ck@324r ti,composite-no-wait-gate-clockžgš$x xauxclk5_src_mux_ck@324rti,composite-mux-clock žghš$y yauxclk5_src_ckrti,composite-clockžxyz zauxclk5_ck@324rti,divider-clockžzœš$€ €auxclkreq0_ck@210r ti,mux-clockž{|}~€šauxclkreq1_ck@214r ti,mux-clockž{|}~€šauxclkreq2_ck@218r ti,mux-clockž{|}~€šauxclkreq3_ck@21cr ti,mux-clockž{|}~€šauxclkreq4_ck@220r ti,mux-clockž{|}~€š auxclkreq5_ck@224r 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compatibleinterrupt-parent#address-cells#size-cellsi2c0i2c1i2c2i2c3serial0serial1serial2serial3display0display1device_typenext-level-cacheregclocksclock-namesclock-latencyoperating-pointscooling-min-levelcooling-max-level#cooling-cellslinux,phandleinterrupt-controller#interrupt-cellscache-unifiedcache-levelinterruptsti,hwmodssramranges#clock-cellsclock-frequencyti,bit-shiftti,max-divti,autoidle-shiftti,index-starts-at-oneti,invert-autoidle-bitclock-multclock-divti,index-power-of-twoti,dividersti,clock-divti,clock-multti,set-rate-parentpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsstatusdmasdma-namesgpmc,num-csgpmc,num-waitpinsti,no-idle-on-initinterrupts-extended#hwlock-cellsregulator-always-onusb-supply#pwm-cells#io-channel-cellsti,audpwron-gpiovio-supplyv2v1-supplyenable-active-highti,spi-num-csti,dual-voltti,needs-special-resetpbias-supplyvmmc-supplybus-widthnon-removablecap-power-off-cardref-clock-frequency#iommu-cellsti,iommu-bus-err-backreg-namesinterrupt-namesti,buffer-sizephy-typehw-caps-read-idle-ctrlhw-caps-ll-interfacehw-caps-temp-alertcs1-useddevice-handlectrl-module#phy-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,timer-alwonti,timer-dspti,timer-pwmport1-modephysusb-phyphy-namesmultipointnum-epsram-bitsinterface-typepowerti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infovdd-supplyvdda-supplyremote-endpointdata-lines#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicedensityio-widthtRPab-min-tcktRCD-min-tcktWR-min-tcktRASmin-min-tcktRRD-min-tcktWTR-min-tcktXP-min-tcktRTP-min-tcktCKE-min-tcktCKESR-min-tcktFAW-min-tckmin-freqmax-freqtRPabtRCDtWRtRAS-mintRRDtWTRtXPtRTPtCKESRtDQSCK-maxtFAWtZQCStZQCLtZQinittRAS-max-nstDQSCK-max-deratedlabelgpioslinux,default-triggerti,modelti,mclk-freqti,mcpdmti,twl6040ti,audio-routingstartup-delay-usregulator-boot-onreset-gpiosvcc-supplypowerdown-gpiosdigitalddc-i2c-bus