8( d*chipspark,popmetal-rk3288rockchip,rk3288&7PopMetal-RK3288chosenaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000memorymemoryarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12`@p@ @OOa sB@ ~ ' 9  K 0 $@29EKcpu@501cpuarm,cortex-a12EKcpu@502cpuarm,cortex-a12EKcpu@503cpuarm,cortex-a12EKamba simple-busSdma-controller@ff250000arm,pl330arm,primecell%@Ze2 apb_pclkEKdma-controller@ff600000arm,pl330arm,primecell`@Ze2 apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@Ze2 apb_pclkEMKMreserved-memorySdma-unusable@fe000000oscillator fixed-clockn6xin24mE K timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 2 a timerpclkdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshcр 2Drvbiuciuciu-driveciu-sample  @okay '8JU_defaultm wdwmmc@ff0d0000rockchip,rk3288-dw-mshcр 2Eswbiuciuciu-driveciu-sample ! @ disableddwmmc@ff0e0000rockchip,rk3288-dw-mshcр 2Ftxbiuciuciu-driveciu-sample "@ disableddwmmc@ff0f0000rockchip,rk3288-dw-mshcр 2Guybiuciuciu-driveciu-sample #@okay JU_defaultmwsaradc@ff100000rockchip,saradc $2I[saradcapb_pclkW saradc-apb disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi2ARspiclkapb_pclk  txrx ,_defaultm disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi2BSspiclkapb_pclk txrx -_defaultm  disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi2CTspiclkapb_pclktxrx ._defaultm!"#$ disabledi2c@ff140000rockchip,rk3288-i2c >i2c2M_defaultm%okayak8963@0dasahi-kasei,ak8975 &&_defaultm'l3g4200d@69st,l3g4200d-gyroimma8452@1d fsl,mma8452&&_defaultm(i2c@ff150000rockchip,rk3288-i2c ?i2c2O_defaultm)okayi2c@ff160000rockchip,rk3288-i2c @i2c2P_defaultm*okayi2c@ff170000rockchip,rk3288-i2c Ai2c2Q_defaultm+okayE^K^serial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 72MUbaudclkapb_pclk_defaultm,okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 82NVbaudclkapb_pclk_defaultm-okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 92OWbaudclkapb_pclk_defaultm.okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :2PXbaudclkapb_pclk_defaultm/okayserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;2QYbaudclkapb_pclk_defaultm0okaythermal-zonesreserve_thermal+91cpu_thermald+91tripscpu_alert0IpUpassiveE2K2cpu_alert1I$UpassiveE3K3cpu_critI_U criticalcooling-mapsmap0`2 emap1`3 egpu_thermald+91tripsgpu_alert0IpUpassiveE4K4gpu_critI_U criticalcooling-mapsmap0`4 etsadc@ff280000rockchip,rk3288-tsadc( %2HZtsadcapb_pclk tsadc-apb_initdefaultsleepm5t6~5sokayE1K1ethernet@ff290000rockchip,rk3288-gmac)macirqeth_wake_irq782fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB stmmacethok8rgmiiinput %95 K'B@`p:_defaultm;0usb@ff500000 generic-ehciP 2usbhost<usb disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 2otghost= usb2-phy disabledusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 2otgotg@@ > usb2-phyokayusb@ff5c0000 generic-ehci\ 2usbhost disabledi2c@ff650000rockchip,rk3288-i2ce <i2c2L_defaultm?okaypmic@1brockchip,rk808&@_defaultmAB xin32krk808-clkout2C%C1C=CICUCaDmyCregulatorsDCDC_REG1 qpvdd_armEKregulator-state-memDCDC_REG2 Pvdd_gpuregulator-state-mem6B@DCDC_REG3vcc_ddrregulator-state-memDCDC_REG42Z2Zvcc_ioEKregulator-state-mem62ZLDO_REG12Z2Zvcc_lanE8K8regulator-state-mem62ZLDO_REG22Z2Z vccio_sdEKregulator-state-memLDO_REG3B@B@vdd_10regulator-state-mem6B@LDO_REG4w@w@ vcc18_lcdregulator-state-mem6w@LDO_REG5w@2Zldo5LDO_REG6B@B@ vdd10_lcdregulator-state-mem6B@LDO_REG7w@w@vcc_18EDKDregulator-state-mem6w@LDO_REG82Z2Zvcca_33EJKJregulator-state-mem62ZSWITCH_REG1 vccio_wlELKLregulator-state-memSWITCH_REG2vcc_lcdregulator-state-memi2c@ff660000rockchip,rk3288-i2cf =i2c2N_defaultmEokaypwm@ff680000rockchip,rk3288-pwmhR_defaultmF2^pwm disabledpwm@ff680010rockchip,rk3288-pwmhR_defaultmG2^pwm disabledpwm@ff680020rockchip,rk3288-pwmh R_defaultmH2^pwm disabledpwm@ff680030rockchip,rk3288-pwmh0R_defaultmI2^pwm disabledbus_intmem@ff700000 mmio-sramp Spsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsEKpower-controller!rockchip,rk3288-power-controller]`hp EPKPpd_vio@9 2chgfdehilkjpd_hevc@11 2oppd_video@12 2pd_gpu@13 2reboot-modesyscon-reboot-modeqxRBRBRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv7H`jk$#gׄeрxhрxhEKsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwE7K7edp-phyrockchip,rk3288-dp-phy2h24m disabledE[K[io-domains"rockchip,rk3288-io-voltage-domainokayJK 8'7CQLusbphyrockchip,rk3288-usb-phyokayusb-phy@320 2]phyclkE>K>usb-phy@33442^phyclkE<K<usb-phy@348H2_phyclkE=K=watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt2p O disabledsound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif] hclkmclk2TMtx 6_defaultmN7 disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s 5MMtxrxi2s_hclki2s_clk2R_defaultmOn disabledcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 2}aclkhclksclkapb_pclk crypto-rstokayvop@ff930000rockchip,rk3288-vop 2aclk_vopdclk_vophclk_vopP def axiahbdclkQokayportE K endpoint@0RE_K_endpoint@1SE\K\endpoint@2TEYKYiommu@ff930300rockchip,iommu  vopb_mmuP okayEQKQvop@ff940000rockchip,rk3288-vop 2aclk_vopdclk_vophclk_vopP  axiahbdclkUokayportE K endpoint@0VE`K`endpoint@1WE]K]endpoint@2XEZKZiommu@ff940300rockchip,iommu  vopl_mmuP okayEUKUmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 2~d refpclkP 7 disabledportsportendpoint@0YETKTendpoint@1ZEXKXdp@ff970000rockchip,rk3288-dp@ b2icdppclk[dpodp7 disabledportsport@0endpoint@0\ESKSendpoint@1]EWKWhdmi@ff980000rockchip,rk3288-dw-hdmi7 g2hm iahbisfrP okay^portsportendpoint@0_ERKRendpoint@1`EVKVmali@ffa300004rockchip,rk3288-maliarm,mali-t760arm,mali-midgard$ jobmmugpu2aP  disabledgpu-opp-tableoperating-points-v2EaKaopp@100000000~opp@200000000 ~opp@300000000B@opp@400000000ׄopp@500000000eOopp@600000000#Finterrupt-controller@ffc01000 arm,gic-400   @ `   EKefuse@ffb40000rockchip,rockchip-efuse 2q pclk_efusecpu_leakage@17pinctrlrockchip,rk3288-pinctrl7Sgpio0@ff750000rockchip,gpio-banku Q2@0@ E@K@gpio1@ff780000rockchip,gpio-bankx R2A0@ gpio2@ff790000rockchip,gpio-banky S2B0@ gpio3@ff7a0000rockchip,gpio-bankz T2C0@ gpio4@ff7b0000rockchip,gpio-bank{ U2D0@ E9K9gpio5@ff7c0000rockchip,gpio-bank| V2E0@ gpio6@ff7d0000rockchip,gpio-bank} W2F0@ gpio7@ff7e0000rockchip,gpio-bank~ X2G0@ EhKhgpio8@ff7f0000rockchip,gpio-bank Y2H0@ E&K&hdmihdmi-ddc Lbbpcfg-pull-upZEcKcpcfg-pull-downgEdKdpcfg-pull-nonevEbKbpcfg-pull-none-12mav EeKesleepglobal-pwroffLbEBKBddrio-pwroffLbddr0-retentionLcddr1-retentionLcedpedp-hpdL di2c0i2c0-xfer LbbE?K?i2c1i2c1-xfer LbbE%K%i2c2i2c2-xfer L b bEEKEi2c3i2c3-xfer LbbE)K)i2c4i2c4-xfer LbbE*K*i2c5i2c5-xfer LbbE+K+i2s0i2s0-bus`LbbbbbbEOKOsdmmcsdmmc-clkLbE K sdmmc-cmdLcE K sdmmc-cdLcEKsdmmc-bus1Lcsdmmc-bus4@LccccEKsdmmc-pwrL bEiKisdio0sdio0-bus1Lcsdio0-bus4@Lccccsdio0-cmdLcsdio0-clkLbsdio0-cdLcsdio0-wpLcsdio0-pwrLcsdio0-bkpwrLcsdio0-intLcsdio1sdio1-bus1Lcsdio1-bus4@Lccccsdio1-cdLcsdio1-wpLcsdio1-bkpwrLcsdio1-intLcsdio1-cmdLcsdio1-clkLbsdio1-pwrL cemmcemmc-clkLbEKemmc-cmdLcEKemmc-pwrL cEKemmc-bus1Lcemmc-bus4@Lccccemmc-bus8LccccccccEKspi0spi0-clkL cEKspi0-cs0L cEKspi0-txLcEKspi0-rxLcEKspi0-cs1Lcspi1spi1-clkL cEKspi1-cs0L cE K spi1-rxLcEKspi1-txLcEKspi2spi2-cs1Lcspi2-clkLcE!K!spi2-cs0LcE$K$spi2-rxLcE#K#spi2-txL cE"K"uart0uart0-xfer LcbE,K,uart0-ctsLcuart0-rtsLbuart1uart1-xfer Lc bE-K-uart1-ctsL cuart1-rtsL buart2uart2-xfer LcbE.K.uart3uart3-xfer LcbE/K/uart3-ctsL cuart3-rtsL buart4uart4-xfer L c bE0K0uart4-ctsLcuart4-rtsLbtsadcotp-gpioL bE5K5otp-outL bE6K6pwm0pwm0-pinLbEFKFpwm1pwm1-pinLbEGKGpwm2pwm2-pinLbEHKHpwm3pwm3-pinLbEIKIgmacrgmii-pinsLbbbbeeeebbb eebbE;K;rmii-pinsLbbbbbbbbbbspdifspdif-txL bENKNak8963comp-intLcE'K'buttonspwrbtnLcEfKfdvpdvp-pwrLbEkKkirir-intLcEgKgmma8452gsensor-intLcE(K(pmicpmic-intLcEAKAexternal-gmac-clock fixed-clocksY@ ext_gmacE:K:gpio-keys gpio-keys_defaultmfpower @tGPIO Key Power dir-receivergpio-ir-receiver @_defaultmgflash-regulatorregulator-fixed vcc_flashw@w@EKsdmmc-regulatorregulator-fixed 0h _defaultmivcc_sd2Z2ZEKvsys-regulatorregulator-fixedvcc_sysLK@LK@ECKCvcc18-dvp-regulatorregulator-fixed vcc18-dvpw@w@jEKKKvcc28-dvp-regulatorregulator-fixed 0@_defaultmk vcc28_dvp**EjKj #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2device_typereginterruptsinterrupt-affinityenable-methodrockchip,pmuresetsoperating-points#cooling-cellsclock-latencyclockscpu0-supplylinux,phandleranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredportsclock-freq-min-maxfifo-depthbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wpnum-slotspinctrl-namespinctrl-0vmmc-supplyvqmmc-supplynon-removable#io-channel-cellsreset-namesdmasdma-namesvdd-supplyvid-supplyst,drdy-int-pinvddio-supplyreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfphy-supplyphy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usassigned-clocksassigned-clock-parentstx_delayrx_delayphysphy-namesdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmarockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-nameregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsaudio-supplybb-supplydvp-supplyflash0-supplyflash1-supplygpio30-supplygpio1830-supplylcdc-supplysdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channelspower-domainsiommusremote-endpoint#iommu-cellsddc-i2c-busoperating-points-v2opp-hzopp-microvoltinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthautorepeatgpioslinux,codelabellinux,input-typedebounce-intervalvin-supplystartup-delay-usenable-active-high