Ð þí#È8!H(€! ,SoPine with baseboard;2pine64,sopine-baseboardpine64,sopineallwinner,sun50i-a64cpus cpu@02arm,cortex-a53arm,armv8=cpuIMpscicpu@12arm,cortex-a53arm,armv8=cpuIMpscicpu@22arm,cortex-a53arm,armv8=cpuIMpscicpu@32arm,cortex-a53arm,armv8=cpuIMpsciosc24M_clk[ 2fixed-clockhn6xosc24M‹‘osc32k_clk[ 2fixed-clockh€xosc32k‹ ‘ internal-osc-clk[ 2fixed-clockhô$™á£xiosc‹ ‘ psci 2arm,psci-0.2Tsmctimer2arm,armv8-timer0¨   soc 2simple-bus ³syscon@1c00000.2allwinner,sun50i-a64-system-controllersysconIÀmmc@1c0f0002allwinner,sun50i-a64-mmcIÀðºKÁahbmmcÍÔahb ¨<àðÑ€îokay õdefault '2mmc@1c100002allwinner,sun50i-a64-mmcIÁº LÁahbmmcÍ Ôahb ¨=àðÑ€ îdisabled mmc@1c110002allwinner,sun50i-a64-emmcIÁº!MÁahbmmcÍ Ôahb ¨>à ëÂîokay õdefault <2Iusb@01c190002allwinner,sun8i-a33-musbIÁº)Í ¨GZmcjousbyîokay€hostphy@01c194002allwinner,sun50i-a64-usb-phyIÁ”Á¨Á¸ˆphy_ctrlpmu0pmu1ºVWÁusb0_phyusb1_phyÍÔusb0_resetusb1_resetîokay’‹‘usb@01c1a000'2allwinner,sun50i-a64-ehcigeneric-ehciIÁ  ¨Hº,*[Íîokayusb@01c1a400'2allwinner,sun50i-a64-ohcigeneric-ohciIÁ¤ ¨Iº,[Íîokayusb@01c1b000'2allwinner,sun50i-a64-ehcigeneric-ehciIÁ° ¨Jº-+]Íjousbîokayusb@01c1b400'2allwinner,sun50i-a64-ohcigeneric-ohciIÁ´ ¨Kº-]Íjousbîokayclock@01c200002allwinner,sun50i-a64-ccuIº  Áhosclosc[‹‘pinctrl@1c208002allwinner,sun50i-a64-pinctrlIÂ$¨ º:ªºÆÛi2c1_pinsìPH2PH3ñi2c1mmc0-pinsìPF0PF1PF2PF3PF4PF5ñmmc0ú ‹‘mmc1-pinsìPG0PG1PG2PG3PG4PG5ñmmc1ú mmc2-pins7ìPC1PC5PC6PC8PC9PC10PC11PC12PC13PC14PC15PC16ñmmc2ú ‹‘rmii_pins2ìPD10PD11PD13PD14PD17PD18PD19PD20PD22PD23ñemacú(rgmii_pinsIìPD8PD9PD10PD11PD12PD13PD15PD16PD17PD18PD19PD20PD21PD22PD23ñemacú(uart0@0ìPB8PB9ñuart0‹ ‘ uart1_pinsìPG6PG7ñuart1uart1_rts_cts_pinsìPG8PG9ñuart1uart2-pinsìPB0PB1ñuart2uart3-pinsìPD0PD1ñuart3uart4-pinsìPD2PD3ñuart4uart4-rts-cts-pinsìPD4PD5ñuart4serial@1c280002snps,dw-apb-uartI€ ¨ ºCÍ.îokayõdefault serial@1c284002snps,dw-apb-uartI„ ¨ ºDÍ/ îdisabledserial@1c288002snps,dw-apb-uartIˆ ¨ ºEÍ0 îdisabledserial@1c28c002snps,dw-apb-uartIÂŒ ¨ ºFÍ1 îdisabledserial@1c290002snps,dw-apb-uartI ¨ ºGÍ2 îdisabledi2c@1c2ac002allwinner,sun6i-a31-i2cI¬ ¨º?Í* îdisabled i2c@1c2b0002allwinner,sun6i-a31-i2cI° ¨º@Í+ îdisabled i2c@1c2b4002allwinner,sun6i-a31-i2cI´ ¨ºAÍ, îdisabled interrupt-controller@1c81000 2arm,gic-400 IÈÈ È@ È`  ¨ ÆÛ‹‘rtc@1f000002allwinner,sun6i-a31-rtcIðT¨()clock@1f014002allwinner,sun50i-a64-r-ccuIðº  Áhoscloscioscpll-periph[‹ ‘ pinctrl@01f02c002allwinner,sun50i-a64-r-pinctrlIð, ¨-º  ÁapbhoscloscªºÆÛrsb@0ìPL0PL1ñs_rsb‹ ‘ rsb@1f034002allwinner,sun8i-a23-rsbIð4 ¨'º h-ÆÀÍ õdefault  îdisabled vcc3v32regulator-fixed-vcc3v3<2Z T2Z ‹‘aliasesl/soc/serial@1c28000chosentserial0:115200n8vcc1v82regulator-fixed-vcc1v8<w@Tw@‹‘ interrupt-parent#address-cells#size-cellsmodelcompatibledevice_typeregenable-method#clock-cellsclock-frequencyclock-output-nameslinux,phandleclock-accuracyinterruptsrangesclocksclock-namesresetsreset-namesmax-frequencystatuspinctrl-namespinctrl-0vmmc-supplynon-removabledisable-wpbus-widthvqmmc-supplycap-mmc-hw-resetinterrupt-namesphysphy-namesextcondr_modereg-names#phy-cells#reset-cellsgpio-controller#gpio-cellsinterrupt-controller#interrupt-cellspinsfunctiondrive-strengthbias-pull-upreg-shiftreg-io-widthregulator-nameregulator-min-microvoltregulator-max-microvoltserial0stdout-path