"m8 ( t3hisilicon,hi3798cv200-poplarhisilicon,hi3798cv200 +#7HiSilicon Poplar Development Boardpsci arm,psci-0.2=smccpus+cpu@0arm,cortex-a53DcpuPTpscicpu@1arm,cortex-a53DcpuPTpscicpu@2arm,cortex-a53DcpuPTpscicpu@3arm,cortex-a53DcpuPTpsciinterrupt-controller@f1001000 arm,gic-400 P bstimerarm,armv8-timer0   soc@f0000000 simple-bus+clock-reset-controller@8a22000,hisilicon,hi3798cv200-crgsysconsimple-mfdP reset-controllerti,syscon-reset8  system-controller@8000000%hisilicon,hi3798cv200-sysctrlsysconPserial@8b00000arm,pl011arm,primecellP 1 apb_pclkokayserial@8b02000arm,pl011arm,primecellP  3 apb_pclkokay LS-UART0i2c@8b10000hisilicon,hix5hd2-i2cP+ &okayLS-I2C0i2c@8b11000hisilicon,hix5hd2-i2cP+ ' disabledi2c@8b12000hisilicon,hix5hd2-i2cP + (okayLS-I2C1i2c@8b13000hisilicon,hix5hd2-i2cP0+ )  disabledi2c@8b14000hisilicon,hix5hd2-i2cP@+ *  disabledspi@8b1a000arm,pl022arm,primecellP -   apb_pclk+okayLS-SPI0mmc@9830000 snps,dw-mshcP  #ciubiugpio@8b20000arm,pl061arm,primecellP l sb apb_pclk disabledgpio@8b21000arm,pl061arm,primecellP m sb apb_pclkokay#,LS-GPIO-ELS-GPIO-FLS-GPIO-Jgpio@8b22000arm,pl061arm,primecellP  n sb apb_pclkokay5,LS-GPIO-HLS-GPIO-ILS-GPIO-LLS-GPIO-GLS-GPIO-Kgpio@8b23000arm,pl061arm,primecellP0 o sb apb_pclkokay,LS-GPIO-CLS-GPIO-Bgpio@8b24000arm,pl061arm,primecellP@ p sb apb_pclkokay,LS-GPIO-Dgpio@8004000arm,pl061arm,primecellP@ q sb apb_pclkokay%,USER-LED-1USER-LED-2LS-GPIO-Agpio@8b26000arm,pl061arm,primecellP` r sb apb_pclkokay,USER-LED-0gpio@8b27000arm,pl061arm,primecellPp s sb apb_pclk disabledgpio@8b28000arm,pl061arm,primecellP t sb apb_pclk disabledgpio@8b29000arm,pl061arm,primecellP u sb apb_pclk disabledgpio@8b2a000arm,pl061arm,primecellP v sb apb_pclkokay,USER-LED-3  gpio@8b2b000arm,pl061arm,primecellP w sb apb_pclk disabledgpio@8b2c000arm,pl061arm,primecellP x sb apb_pclk disabledethernet@98400002hisilicon,hi3798cv200-gmachisilicon,hisi-gmac-v2P  0  Gmac_coremac_ifc < Cmac_coremac_ifcphy disabledethernet@98410002hisilicon,hi3798cv200-gmachisilicon,hisi-gmac-v2P  0 H mac_coremac_ifc <  Cmac_coremac_ifcphyokay+OZrgmii c''u0phy@3Pir@8001000hisilicon,hix5hd2-irP /okayaliases/soc@f0000000/serial@8b00000/soc@f0000000/serial@8b02000chosenserial0:115200n8memory@0DmemoryPleds gpio-ledsuser-led0 USER-LED0   heartbeatoffuser-led1 USER-LED1  mmc0offuser-led2 USER-LED2  noneoffuser-led3 USER-LED3  cpu0off compatibleinterrupt-parent#address-cells#size-cellsmodelmethoddevice_typeregenable-method#interrupt-cellsinterrupt-controllerlinux,phandleinterruptsranges#clock-cells#reset-cellsti,reset-bitsclocksclock-namesstatuslabelclock-frequencynum-cscs-gpiosgpio-controller#gpio-cellsgpio-line-namesresetsreset-namesphy-handlephy-modehisilicon,phy-reset-delays-usserial0serial2stdout-pathlinux,default-triggerdefault-state