8~(~(hisilicon,hi6220-hikeyhisilicon,hi6220 +7HiKey Development Boardpsci arm,psci-0.2=smccpus+cpu-mapcluster0core0Dcore1Dcore2Dcore3Dcluster1core0Dcore1Dcore2Dcore3D idle-statesHpscicpu-sleeparm,idle-stateUf}  cluster-sleeparm,idle-stateUf} cpu@0arm,cortex-a53arm,armv8cpupsci   +=L \7cpu@1arm,cortex-a53arm,armv8cpupsci  L cpu@2arm,cortex-a53arm,armv8cpupsci  L cpu@3arm,cortex-a53arm,armv8cpupsci  L cpu@100arm,cortex-a53arm,armv8cpupsci L cpu@101arm,cortex-a53arm,armv8cpupsci L cpu@102arm,cortex-a53arm,armv8cpupsci L cpu@103arm,cortex-a53arm,armv8cpupsci L   l2-cache0cache  l2-cache1cachecpu_opp_tableoperating-points-v2v  opp00 eހ opp01ހ opp02+s@ opp0398p` opp04GKP interrupt-controller@f6801000 arm,gic-400@ @ `   timerarm,armv8-timer 0   soc simple-bus+sram@fff80000!hisilicon,hi6220-sramctrlsyscon ao_ctrl@f7800000hisilicon,hi6220-aoctrlsyscon sys_ctrl@f7030000 hisilicon,hi6220-sysctrlsyscon media_ctrl@f4410000"hisilicon,hi6220-mediactrlsysconATTpm_ctrl@f7032000hisilicon,hi6220-pmctrlsyscon medianoc_ade@f4520000sysconR@SSstub_clockhisilicon,hi6220-stub-clkmbox-tx   uart@f8015000arm,pl011arm,primecellP $$$%uartclkapb_pclkuart@f7111000arm,pl011arm,primecell %%uartclkapb_pclk1default ?IokP)`рbluetooth ti,wl1835-st u %ext_clockuart@f7112000arm,pl011arm,primecell  &%uartclkapb_pclk1default?Iok LS-UART0uart@f7113000arm,pl011arm,primecell0 '%uartclkapb_pclk1default?Iok LS-UART1uart@f7114000arm,pl011arm,primecell@ (%uartclkapb_pclk1default? Idisableddma@f7370000hisilicon,k3-dma-1.07  T  hi6220_dmaIokOOtimer@f8008000arm,sp804arm,primecell%timer1timer2apb_pclkrtc@f8003000arm,pl031arm,primecell0  % %apb_pclkrtc@f8004000arm,pl031arm,primecell@ & %apb_pclkpinmux@f7010000pinctrl-single|+ pPX`hpx!+08Jz~1default? !"#$++gpio-range7boot_sel_pmx_funcX  emmc_pmx_funcPX  $::sd_pmx_func0X  ??sd_pmx_idle0X  BBsdio_pmx_func0X(,048<GGsdio_pmx_idle0X(,048<JJisp_pmx_funcX$(,048<@DHLPTX\`hkadc_ssi_pmx_funcXh!!codec_clk_pmx_funcXl""codec_pmx_func Xptx|fm_pmx_func Xbt_pmx_func Xpwm_in_pmx_funcX##bl_pwm_pmx_funcX$$uart0_pmx_funcXuart1_pmx_func Xuart2_pmx_func Xuart3_pmx_func Xuart4_pmx_func Xuart5_pmx_funcXi2c0_pmx_funcX//i2c1_pmx_funcX11i2c2_pmx_funcX33spi0_pmx_func X,,pinmux@f7010800pinconf-single+ 1default?%&'()boot_sel_cfg_funcXlp%%hkadc_ssi_cfg_funcXllp&&emmc_clk_cfg_funcXl p;;emmc_cfg_funcHX  $(lp<<emmc_rst_cfg_funcX,lp==sd_clk_cfg_funcX l0p@@sd_clk_cfg_idleX lpCCsd_cfg_func(X l pAAsd_cfg_idle(X lpDDsdio_clk_cfg_funcX4l pHHsdio_clk_cfg_idleX4lpKKsdio_cfg_func(X8<@DHlpIIsdio_cfg_idle(X8<@DHlpLLisp_cfg_func1xX(,048<@DHLPX\`dlpisp_cfg_idle1X48lpisp_cfg_func2XTlpcodec_clk_cfg_funcXplp''codec_clk_cfg_idleXplpcodec_cfg_func1Xtlpcodec_cfg_func2Xx|lpcodec_cfg_idle2Xx|lpfm_cfg_func Xlpbt_cfg_func Xlpbt_cfg_idle Xlppwm_in_cfg_funcXlp((bl_pwm_cfg_funcXlp))uart0_cfg_func1Xlpuart0_cfg_func2Xlpuart1_cfg_func1Xlpuart1_cfg_func2Xlpuart2_cfg_func Xlpuart3_cfg_func Xlpuart4_cfg_func Xlpuart5_cfg_funcXlpi2c0_cfg_funcXlp00i2c1_cfg_funcXlp22i2c2_cfg_funcXlp44spi0_cfg_func Xlp--pinmux@f8001800pinconf-singlex+ 1default?*rstout_n_cfg_funcXlp**pmu_peri_en_cfg_funcXlpsysclk0_en_cfg_funcXlpjtag_tdo_cfg_funcX l prf_reset_cfg_funcXptlpgpio@f8011000arm,pl061arm,primecell 4 %apb_pclkOPWR_HOLDDSI_SELUSB_HUB_RESET_NUSB_SELHDMI_PDWL_REG_ONPWRON_DET5V_HUB_EN55gpio@f8012000arm,pl061arm,primecell  5 %apb_pclk:SD_DETHDMI_INTPMU_IRQ_NWL_HOST_WAKENCNCNCBT_REG_ONgpio@f8013000arm,pl061arm,primecell0 6 %apb_pclkBGPIO-AGPIO-BGPIO-CGPIO-DGPIO-EUSB_ID_DETUSB_VBUS_DETGPIO-Hgpio@f8014000arm,pl061arm,primecell@ 7+P %apb_pclk%GPIO3_0NCNCNCWLAN_ACTIVENCNCZZgpio@f7020000arm,pl061arm,primecell 8+X %apb_pclk?USER_LED1USER_LED2USER_LED3USER_LED4SD_SELNCNCBT_ACTIVEYYgpio@f7021000arm,pl061arm,primecell 9+` %apb_pclk?NCNC[UART1_RxD][UART1_TxD][AUX_SSI1]NC[PCM_CLK][PCM_FS]gpio@f7022000arm,pl061arm,primecell  :+h %apb_pclk=[SPI0_DIN][SPI0_DOUT][SPI0_CS][SPI0_SCLK]NCNCNCGPIO-G..gpio@f7023000arm,pl061arm,primecell0 ;+p %apb_pclk$NCNCNCNC[PCM_DI][PCM_DO]NCNCgpio@f7024000arm,pl061arm,primecell@ < +x+ %apb_pclkNC[CEC_CLK_19_2MHZ]NCgpio@f7025000arm,pl061arm,primecellP =+ %apb_pclk'GPIO-JGPIO-LNCNCNCNC[ISP_CCLK0]gpio@f7026000arm,pl061arm,primecell` > ++ %apb_pclk?BOOT_SEL[ISP_CCLK1]GPIO-IGPIO-KNCNC[I2C2_SDA][I2C2_SCL]gpio@f7027000arm,pl061arm,primecellp ? ++ %apb_pclk"[I2C3_SDA][I2C3_SCL]NCNCNCgpio@f7028000arm,pl061arm,primecell @ +!++ %apb_pclk8[BT_PCM_XFS][BT_PCM_DI][BT_PCM_DO]NCNCNCNCGPIO-Fgpio@f7029000arm,pl061arm,primecell A+0 %apb_pclkh[UART0_RX][UART0_TX][BT_UART1_CTS][BT_UART1_RTS][BT_UART1_RX][BT_UART1_TX][UART0_CTS][UART0_RTS]gpio@f702a000arm,pl061arm,primecell B+8 %apb_pclkZ[UART0_RxD][UART0_TxD][I2C0_SCL][I2C0_SDA][I2C1_SCL][I2C1_SDA][I2C2_SCL][I2C2_SDA]gpio@f702b000arm,pl061arm,primecell C0+J+z+~ %apb_pclk NCgpio@f702c000arm,pl061arm,primecell D+ %apb_pclkgpio@f702d000arm,pl061arm,primecell E+ %apb_pclkgpio@f702e000arm,pl061arm,primecell F+ %apb_pclkgpio@f702f000arm,pl061arm,primecell G+ %apb_pclkspi@f7106000arm,pl022arm,primecell` 2 %apb_pclk1default?,-  .Ioki2c@f7100000snps,designware-i2c , ,1default?/0Ioki2c@f7101000snps,designware-i2c -,1default?12Ioki2c@f7102000snps,designware-i2c  .,1default?34Iok+adv7533@39 adi,adv75339  159Gports+port@0endpointX6WWport@2endpointX7PPusbphyhisilicon,hi6220-usb-phyhs8~99usb@f72c0000hisilicon,hi6220-usb,9 usb2-phy%otgotg Mmailbox@f7510000hisilicon,hi6220-mbox Q ^dwmmc0@f723d000hisilicon,hi6220-dw-mshc# H%ciubiureset1default?:;<= *>dwmmc1@f723e000hisilicon,hi6220-dw-mshc~# I+%ciubiureset 1defaultidle ??@A 6BCD@Rcp}E*F  dwmmc2@f723f000hisilicon,hi6220-dw-mshc# J%ciubiureset 1defaultidle ?GHI 6JKL *MN+wlcore@2 ti,wl1835 tsensor@0,f7030700hisilicon,tsensor  %thermal_clkQQi2s@f7118000hisilicon,hi6210-i2s { 8%dacodeci2s-baseOOrxtxGportsport@0[[endpointXPi2s77thermal-zonescls0 d# 5Qtripstrip-point@0EQpassivetrip-point@1E$QpassiveRRcooling-mapsmap0\R aade@f4100000hisilicon,hi6220-adex pade_basezST sTTT(%clk_ade_coreclk_codec_jpegclk_ade_pixPTT`u**IokportendpointXUVVdsi@f4107800hisilicon,hi6220-dsixT%pclkIokports+port@0endpointXVUUport@1endpoint@0XW66debug@f6590000&arm,coresight-cpu-debugarm,primecellY; %apb_pclkDdebug@f6592000&arm,coresight-cpu-debugarm,primecellY ; %apb_pclkDdebug@f6594000&arm,coresight-cpu-debugarm,primecellY@; %apb_pclkDdebug@f6596000&arm,coresight-cpu-debugarm,primecellY`; %apb_pclkDdebug@f65d0000&arm,coresight-cpu-debugarm,primecell]; %apb_pclkDdebug@f65d2000&arm,coresight-cpu-debugarm,primecell] ; %apb_pclkDdebug@f65d4000&arm,coresight-cpu-debugarm,primecell]@; %apb_pclkDdebug@f65d6000&arm,coresight-cpu-debugarm,primecell]`; %apb_pclkD aliases/soc/uart@f8015000/soc/uart@f7111000/soc/uart@f7112000/soc/uart@f7113000chosenserial3:115200n8memory@0memory` `A"reserved-memory+ramoops@0x21f00000ramoops!linux,cmashared-dma-poolreboot-mode-syscon@5f01000sysconsimple-mfdreboot-modesyscon-reboot-modewfUwfU+wfUregulator@0regulator-fixed9SYS_5VHLK@`LK@xXXregulator@1regulator-fixed9VDD_3V3H2Z`2ZxXMMregulator@2regulator-fixed95V_HUBHLK@`LK@x 45X88wl1835-pwrseqmmc-pwrseq-simple 5 %ext_clock NNleds gpio-ledsuser_led4 user_led4 |Y heartbeatuser_led3 user_led3 |Ymmc0user_led2 user_led2 |Ymmc1user_led1 user_led1 |Ycpu0wlan_active_led wifi_active |Zphy0txoffbt_active_led bt_active |Yhci0rxoffpmic@f8000000hisilicon,hi655x-pmic regulatorsLDO2 9LDO2_2V8H&%`0xLDO7 9LDO7_SDIOHw@`2ZxEELDO10 9LDO10_2V85Hw@`-hFFLDO13 9LDO13_1V8Hj`0xLDO14 9LDO14_2V8H&%`0xLDO15 9LDO15_1V8Hj`0xxLDO17 9LDO17_2V5H&%`0xLDO19 9LDO19_3V0Hw@`-h>>LDO21 9LDO21_1V8H-P`xLDO22 9LDO22_1V2H `Oxxfirmwareopteelinaro,optee-tz=smcsound_cardaudio-graph-card[ compatibleinterrupt-parent#address-cells#size-cellsmodelmethodcpuentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uslinux,phandlewakeup-latency-usdevice_typeregenable-methodnext-level-cacheclocksoperating-points-v2cooling-min-levelcooling-max-level#cooling-cellscpu-idle-statesdynamic-power-coefficientopp-sharedopp-hzopp-microvoltclock-latency-ns#interrupt-cellsinterrupt-controllerinterruptsranges#clock-cells#reset-cellshisilicon,hi6220-clk-srammbox-namesmboxesclock-namespinctrl-namespinctrl-0statusassigned-clocksassigned-clock-ratesenable-gpioslabel#dma-cellsdma-channelsdma-requestsdma-no-ccidma-type#pinctrl-cells#gpio-range-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,gpio-range#pinctrl-single,gpio-range-cellspinctrl-single,pinspinctrl-single,bias-pulldownpinctrl-single,bias-pulluppinctrl-single,drive-strengthgpio-controller#gpio-cellsgpio-line-namesgpio-rangesbus-idenable-dmanum-cscs-gpiosi2c-sda-hold-time-nspd-gpioadi,dsi-lanes#sound-dai-cellsremote-endpoint#phy-cellsphy-supplyhisilicon,peripheral-sysconphysphy-namesdr_modeg-rx-fifo-sizeg-np-tx-fifo-sizeg-tx-fifo-size#mbox-cellsresetsreset-namescap-mmc-highspeednon-removablebus-widthvmmc-supplypinctrl-1card-detect-delaycap-sd-highspeedsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50vqmmc-supplydisable-wpcd-gpiosmmc-pwrseq#thermal-sensor-cellsdmasdma-nameshisilicon,sysctrl-syscondai-formatpolling-delaypolling-delay-passivesustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicereg-nameshisilicon,noc-syscondma-coherentserial0serial1serial2serial3stdout-pathrecord-sizeconsole-sizeftrace-sizereusablelinux,cma-defaultoffsetmode-normalmode-bootloadermode-recoveryregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onregulator-always-onvin-supplyreset-gpiospower-off-delay-uslinux,default-triggerdefault-statepmic-gpiosregulator-enable-ramp-delaydais