Iu8Fx(F@$rockchip,rk3328-evbrockchip,rk3328 +7Rockchip RK3328 EVBaliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000cpus+cpu@0icpuarm,cortex-a53arm,armv8uypscicpu@1icpuarm,cortex-a53arm,armv8uypscicpu@2icpuarm,cortex-a53arm,armv8uypscicpu@3icpuarm,cortex-a53arm,armv8uypscil2-cache0cacheamba simple-bus+dmac@ff1f0000arm,pl330arm,primecellu@y apb_pclkarm-pmuarm,cortex-a53-pmu0defgpsciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0   xin24m fixed-clockn6xin24msyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfdu+power-controller!rockchip,rk3328-power-controller+pd_hevc@6upd_video@5upd_vpu@8ureboot-modesyscon-reboot-mode-4RB@RBNRB ^RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uartu 7y&baudclkapb_pclkjodefault }  disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uartu 8y'sclk_uartpclk_uartjodefault }  disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uartu 9y(baudclkapb_pclkjodefault}okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2cu $+y7 i2cpclkodefault} disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2cu %+y8 i2cpclkodefault} disabledi2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2cu &+y9 i2cpclkodefault} disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2cu '+y: i2cpclkodefault} disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spiu 1+y spiclkapb_pclkj txrxodefault} disabledwatchdog@ff1a0000 snps,dw-wdtu (adc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradcu( Py%saradcapb_pclkV saradc-apb disabledclock-controller@ff440000(rockchip,rk3328-crurockchip,crusysconuDx=&'(ABDC"\5H4$z|n6n6n6n6#FLGрxhxhрxhxhdwmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcuP@  y=!JNbiuciuciu_drvciu_sample* disableddwmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcuQ@  y>"KObiuciuciu_drvciu_sample* disableddwmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcuR@  y?#LPbiuciuciu_drvciu_sample* disabledethernet@ff540000rockchip,rk3328-gmacuT 5macirq8ydWXZYMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macc stmmaceth disabledinterrupt-controller@ff811000 arm,gic-400EV@u @ `   pinctrlrockchip,rk3328-pinctrl+gpio0@ff210000rockchip,gpio-banku! 3yk{VEgpio1@ff220000rockchip,gpio-banku" 4yk{VEgpio2@ff230000rockchip,gpio-banku# 5yk{VEgpio3@ff240000rockchip,gpio-banku$ 6yk{VEpcfg-pull-uppcfg-pull-down$$pcfg-pull-nonepcfg-pull-none-2ma##pcfg-pull-up-2mapcfg-pull-up-4mapcfg-pull-none-4mapcfg-pull-down-4mapcfg-pull-none-8mapcfg-pull-up-8ma  pcfg-pull-none-12ma !!pcfg-pull-up-12ma ""pcfg-output-highpcfg-output-lowpcfg-input-highpcfg-inputi2c0i2c0-xfer i2c1i2c1-xfer i2c2i2c2-xfer  i2c3i2c3-xfer i2c3-gpio hdmi_i2chdmii2c-xfer tsadcotp-gpio otp-out uart0uart0-xfer    uart0-cts   uart0-rts   uart0-rts-gpio uart1uart1-xfer   uart1-cts  uart1-rtsuart1-rts-gpiouart2-0uart2m0-xfer uart2-1uart2m1-xfer spi0-0spi0m0-clkspi0m0-cs0 spi0m0-tx spi0m0-rx spi0m0-cs1 spi0-1spi0m1-clkspi0m1-cs0spi0m1-txspi0m1-rxspi0m1-cs1spi0-2spi0m2-clkspi0m2-cs0spi0m2-txspi0m2-rxi2s1i2s1-mclki2s1-sclki2s1-lrckrxi2s1-lrcktxi2s1-sdii2s1-sdoi2s1-sdio1i2s1-sdio2i2s1-sdio3i2s1-sleepi2s2-0i2s2m0-mclki2s2m0-sclki2s2m0-lrckrxi2s2m0-lrcktxi2s2m0-sdii2s2m0-sdoi2s2m0-sleep`i2s2-1i2s2m1-mclki2s2m1-sclki2sm1-lrckrxi2s2m1-lrcktxi2s2m1-sdii2s2m1-sdoi2s2m1-sleepPspdif-0spdifm0-txspdif-1spdifm1-txspdif-2spdifm2-txsdmmc0-0sdmmc0m0-pwrensdmmc0m0-gpiosdmmc0-1sdmmc0m1-pwrensdmmc0m1-gpiosdmmc0sdmmc0-clksdmmc0-cmdsdmmc0-dectnsdmmc0-wrprtsdmmc0-bus1sdmmc0-bus4@sdmmc0-gpiosdmmc0extsdmmc0ext-clksdmmc0ext-cmdsdmmc0ext-wrprtsdmmc0ext-dectnsdmmc0ext-bus1sdmmc0ext-bus4@sdmmc0ext-gpiosdmmc1sdmmc1-clk sdmmc1-cmd  sdmmc1-pwren sdmmc1-wrprt sdmmc1-dectn sdmmc1-bus1 sdmmc1-bus4@    sdmmc1-gpio  emmcemmc-clk!emmc-cmd"emmc-pwrenemmc-rstnoutemmc-bus1"emmc-bus4@""""emmc-bus8""""""""pwm0pwm0-pinpwm1pwm1-pinpwm2pwm2-pinpwmirpwmir-pingmac-1rgmiim1-pins` ! ##!### # #! !##!! rmiim1-pins#!#### # #! !  gmac2phyfephyled-speed100fephyled-speed10fephyled-duplexfephyled-rxm0fephyled-txm0fephyled-linkm0fephyled-rxm1fephyled-txm1fephyled-linkm1tsadc_pintsadc-int tsadc-gpio hdmi_pinhdmi-cechdmi-hpd$cif-0dvp-d2d9-m0   cif-1dvp-d2d9-m1chosenserial2:1500000n8 compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3device_typeregclocksenable-methodnext-level-cachelinux,phandlerangesinterruptsclock-names#dma-cellsinterrupt-affinity#clock-cellsclock-frequencyclock-output-names#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderdmaspinctrl-namespinctrl-0reg-io-widthreg-shiftstatusdma-names#io-channel-cellsresetsreset-namesrockchip,grf#reset-cellsassigned-clocksassigned-clock-parentsassigned-clock-ratesfifo-depthinterrupt-names#interrupt-cellsinterrupt-controllergpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-path