^8X(X#geekbuying,geekboxrockchip,rk3368 +7GeekBoxaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff660000Q/i2c@ff140000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/serial@ff180000m/serial@ff190000u/serial@ff690000}/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1core2core3 cpu@0cpuarm,cortex-a53arm,armv8pscicpu@1cpuarm,cortex-a53arm,armv8pscicpu@2cpuarm,cortex-a53arm,armv8pscicpu@3cpuarm,cortex-a53arm,armv8psci  cpu@100cpuarm,cortex-a53arm,armv8pscicpu@101cpuarm,cortex-a53arm,armv8pscicpu@102cpuarm,cortex-a53arm,armv8pscicpu@103cpuarm,cortex-a53arm,armv8psciamba simple-bus+dma-controller@ff250000arm,pl330arm,primecell%@  apb_pclkdma-controller@ff600000arm,pl330arm,primecell`@  apb_pclk44arm-pmuarm,armv8-pmuv3`pqrstuvw & psci arm,psci-0.2smctimerarm,armv8-timer0   oscillator fixed-clock9n6Ixin24m\dwmmc@ff0c00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @iр   D r vbiuciuciu-driveciu-samplew  reset disableddwmmc@ff0d00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @iр   E s wbiuciuciu_drvciu_samplew ! reset disableddwmmc@ff0f00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc@iр   G u ybiuciuciu-driveciu-samplew # resetokay9р  default  saradc@ff100000rockchip,saradc $  I [saradcapb_pclk W saradc-apb disabledspi@ff110000(rockchip,rk3368-spirockchip,rk3066-spi A Rspiclkapb_pclk ,default+ disabledspi@ff120000(rockchip,rk3368-spirockchip,rk3066-spi B Sspiclkapb_pclk -default+ disabledspi@ff130000(rockchip,rk3368-spirockchip,rk3066-spi C Tspiclkapb_pclk )default+ disabledi2c@ff140000(rockchip,rk3368-i2crockchip,rk3288-i2c >+i2c Ndefault disabledi2c@ff150000(rockchip,rk3368-i2crockchip,rk3288-i2c ?+i2c Odefault disabledi2c@ff160000(rockchip,rk3368-i2crockchip,rk3288-i2c @+i2c Pdefault disabledi2c@ff170000(rockchip,rk3368-i2crockchip,rk3288-i2c A+i2c Qdefault disabledserial@ff180000&rockchip,rk3368-uartsnps,dw-apb-uart9n6 M Ubaudclkapb_pclk 7( disabledserial@ff190000&rockchip,rk3368-uartsnps,dw-apb-uart9n6 N Vbaudclkapb_pclk 8( disabledserial@ff1b0000&rockchip,rk3368-uartsnps,dw-apb-uart9n6 P Xbaudclkapb_pclk :( disabledserial@ff1c0000&rockchip,rk3368-uartsnps,dw-apb-uart9n6 Q Ybaudclkapb_pclk ;( disabledthermal-zonescpu5dKY tripscpu_alert0i$upassive!!cpu_alert1i8upassive""cpu_critisu criticalcooling-mapsmap0! map1" gpu5dKY tripsgpu_alert0i8upassive##gpu_criti8u criticalcooling-mapsmap0# tsadc@ff280000rockchip,rk3368-tsadc( % H Ztsadcapb_pclk  tsadc-apbinitdefaultsleep$%$sokay  ethernet@ff290000rockchip,rk3368-gmac) macirq&8  f g c ]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macokay$'/rgmii8inputE U(default)l0uusb@ff500000 generic-ehciP  usbhostokayusb@ff5800002rockchip,rk3368-usbrockchip,rk3066-usbsnps,dwc2X  otg~otg@@ okayi2c@ff650000(rockchip,rk3368-i2crockchip,rk3288-i2ce Li2c <default*+okaypmic@1brockchip,rk808default+, -...... +.7.D.Q Ixin32krk808-clkout2\regulatorsDCDC_REG1^r ``vdd_cpuDCDC_REG2^r ``vdd_logDCDC_REG3^rvcc_ddrDCDC_REG4^r2Z2Zvcc_io  LDO_REG1^rw@w@ vcc18_flash  LDO_REG2^r2Z2Z vcc33_lcdLDO_REG3^rB@B@vdd_10LDO_REG4rw@w@vcca_18LDO_REG5^rw@2Z vccio_sdLDO_REG6^rB@B@ vdd10_lcdLDO_REG7^rw@w@vcc_18LDO_REG8^rw@w@ vcc18_lcdSWITCH_REG1vcc_sdSWITCH_REG2^rvcc_lan''i2c@ff660000(rockchip,rk3368-i2crockchip,rk3288-i2cf =+i2c Mdefault/ disabledpwm@ff680000(rockchip,rk3368-pwmrockchip,rk3288-pwmhdefault0 _pwm disabledpwm@ff680010(rockchip,rk3368-pwmrockchip,rk3288-pwmhdefault1 _pwm disabledpwm@ff680020(rockchip,rk3368-pwmrockchip,rk3288-pwmh  _pwm disabledpwm@ff680030(rockchip,rk3368-pwmrockchip,rk3288-pwmh0default2 _pwm disabledserial@ff690000&rockchip,rk3368-uartsnps,dw-apb-uarti O Wbaudclkapb_pclk 9default3(okaymbox@ff6b0000rockchip,rk3368-mailboxk0 E pclk_mailbox disabledsyscon@ff738000)rockchip,rk3368-pmugrfsysconsimple-mfds66io-domains&rockchip,rk3368-pmu-io-voltage-domain disabledreboot-modesyscon-reboot-modeRBRBRB  RBclock-controller@ff760000rockchip,rk3368-cruv&\  syscon@ff770000&rockchip,rk3368-grfsysconsimple-mfdw&&io-domains"rockchip,rk3368-io-voltage-domain disabledwatchdog@ff800000 rockchip,rk3368-wdtsnps,dw-wdt p Ookaytimer@ff810000,rockchip,rk3368-timerrockchip,rk3288-timer  Bi2s-2ch@ff890000(rockchip,rk3368-i2srockchip,rk3066-i2s (i2s_clki2s_hclk T $44)txrx disabledi2s-8ch@ff898000(rockchip,rk3368-i2srockchip,rk3066-i2s 5i2s_clki2s_hclk R $44)txrxdefault5 disabledinterrupt-controller@ffb71000 arm,gic-4003H@ @ `   pinctrlrockchip,rk3368-pinctrl&Y6+gpio0@ff750000rockchip,gpio-banku @ Qfv3H--gpio1@ff780000rockchip,gpio-bankx A Rfv3Hgpio2@ff790000rockchip,gpio-banky B Sfv3H==gpio3@ff7a0000rockchip,gpio-bankz C Tfv3H::pcfg-pull-up88pcfg-pull-downpcfg-pull-none77pcfg-pull-none-12ma 99emmcemmc-clk7  emmc-cmd8emmc-pwr8emmc-bus18emmc-bus4@8888emmc-bus888888888gmacrgmii-pins7779 9 999 9777777))rmii-pins7779 9 97777i2c0i2c0-xfer 77**i2c1i2c1-xfer 77//i2c2i2c2-xfer  77i2c3i2c3-xfer 77i2c4i2c4-xfer 77i2c5i2c5-xfer 77i2si2s-8ch-bus 7 7777777755pwm0pwm0-pin700pwm1pwm1-pin711pwm3pwm3-pin722sdio0sdio0-bus18sdio0-bus4@8888sdio0-cmd8sdio0-clk7sdio0-cd8sdio0-wp8sdio0-pwr8sdio0-bkpwr8sdio0-int8sdmmcsdmmc-clk 7sdmmc-cmd 8sdmmc-cd 8sdmmc-bus18sdmmc-bus4@8888spi0spi0-clk8spi0-cs08spi0-cs18spi0-tx8spi0-rx8spi1spi1-clk8spi1-cs08spi1-cs18spi1-rx8spi1-tx8spi2spi2-clk 8spi2-cs0 8spi2-rx 8spi2-tx 8tsadcotp-gpio7$$otp-out7%%uart0uart0-xfer 87uart0-cts7uart0-rts7uart1uart1-xfer 87uart1-cts7uart1-rts7uart2uart2-xfer 8733uart3uart3-xfer 87uart3-cts7uart3-rts7uart4uart4-xfer 87uart4-cts7uart4-rts7irir-int7;;keyspwr-key7<<pmicpmic-sleep7,,pmic-int8++chosenserial2:115200n8memory@0memorygmac-clk fixed-clock9sY@ Iext_gmac\((ir-receivergpio-ir-receiver :default;gpio-keys gpio-keysdefault<power - GPIO Powertgpio-leds gpio-ledsblue =geekbox:blue:ledonred =geekbox:red:ledoffvcc-sys-regulatorregulator-fixedvcc_sysLK@LK@^r.. compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2cpudevice_typeregenable-method#cooling-cellslinux,phandlerangesinterrupts#dma-cellsarm,pl330-broken-no-flushpclocksclock-namesinterrupt-affinityclock-frequencyclock-output-names#clock-cellsmax-frequencyfifo-depthresetsreset-namesstatusbus-widthcap-mmc-highspeeddisable-wpnon-removablenum-slotsvmmc-supplyvqmmc-supplypinctrl-namespinctrl-0#io-channel-cellsreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfphy-supplyphy-modeclock_in_outassigned-clocksassigned-clock-parentstx_delayrx_delaydr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-name#pwm-cells#mbox-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsdmasdma-namesinterrupt-controller#interrupt-cellsrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsstdout-pathgpioslabellinux,codewakeup-sourcedefault-state