_8X(tXh.rockchip,px5-evbrockchip,px5rockchip,rk3368 +7Rockchip PX5 EVBaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff660000Q/i2c@ff140000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/serial@ff180000m/serial@ff190000u/serial@ff690000}/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1core2core3 cpu@0cpuarm,cortex-a53arm,armv8pscicpu@1cpuarm,cortex-a53arm,armv8pscicpu@2cpuarm,cortex-a53arm,armv8pscicpu@3cpuarm,cortex-a53arm,armv8psci  cpu@100cpuarm,cortex-a53arm,armv8pscicpu@101cpuarm,cortex-a53arm,armv8pscicpu@102cpuarm,cortex-a53arm,armv8pscicpu@103cpuarm,cortex-a53arm,armv8psciamba simple-bus+dma-controller@ff250000arm,pl330arm,primecell%@  apb_pclkdma-controller@ff600000arm,pl330arm,primecell`@  apb_pclk99arm-pmuarm,armv8-pmuv3`pqrstuvw & psci arm,psci-0.2smctimerarm,armv8-timer0   oscillator fixed-clock9n6Ixin24m\dwmmc@ff0c00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @iр   D r vbiuciuciu-driveciu-samplew  resetokaydefault 'ZEQdwmmc@ff0d00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @iр   E s wbiuciuciu_drvciu_samplew ! reset disableddwmmc@ff0f00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc@iр   G u ybiuciuciu-driveciu-samplew # resetokay9р^idefault EQsaradc@ff100000rockchip,saradc $ I [saradcapb_pclk W saradc-apb disabledspi@ff110000(rockchip,rk3368-spirockchip,rk3066-spi A Rspiclkapb_pclk ,default+ disabledspi@ff120000(rockchip,rk3368-spirockchip,rk3066-spi B Sspiclkapb_pclk -default+ disabledspi@ff130000(rockchip,rk3368-spirockchip,rk3066-spi C Tspiclkapb_pclk )default !+ disabledi2c@ff140000(rockchip,rk3368-i2crockchip,rk3288-i2c >+i2c Ndefault"okaytouchscreen@40silead,gsl1680@ # # i2c@ff150000(rockchip,rk3368-i2crockchip,rk3288-i2c ?+i2c Odefault$ disabledi2c@ff160000(rockchip,rk3368-i2crockchip,rk3288-i2c @+i2c Pdefault% disabledi2c@ff170000(rockchip,rk3368-i2crockchip,rk3288-i2c A+i2c Qdefault& disabledserial@ff180000&rockchip,rk3368-uartsnps,dw-apb-uart9n6 M Ubaudclkapb_pclk 7 disabledserial@ff190000&rockchip,rk3368-uartsnps,dw-apb-uart9n6 N Vbaudclkapb_pclk 8 disabledserial@ff1b0000&rockchip,rk3368-uartsnps,dw-apb-uart9n6 P Xbaudclkapb_pclk : disabledserial@ff1c0000&rockchip,rk3368-uartsnps,dw-apb-uart9n6 Q Ybaudclkapb_pclk ;okaythermal-zonescpud&4'tripscpu_alert0D$Ppassive((cpu_alert1D8Ppassive))cpu_critDsP criticalcooling-mapsmap0[( `map1[) `gpud&4'tripsgpu_alert0D8Ppassive**gpu_critD8P criticalcooling-mapsmap0[* `tsadc@ff280000rockchip,rk3368-tsadc( % H Ztsadcapb_pclk  tsadc-apbinitdefaultsleep+o,y+sokay''ethernet@ff290000rockchip,rk3368-gmac) macirq-8  f g c ]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac disabledusb@ff500000 generic-ehciP  usbhostokayusb@ff5800002rockchip,rk3368-usbrockchip,rk3066-usbsnps,dwc2X  otgotg(@@ okayi2c@ff650000(rockchip,rk3368-i2crockchip,rk3288-i2ce Li2c <default.+okaypmic@1brockchip,rk808 /default017X2d2p2|222222Ixin32krk808-clkout2\regulatorsDCDC_REG1 ``5vdd_cpuDCDC_REG2 ``5vdd_logDCDC_REG35vcc_ddrDCDC_REG42Z2Z5vcc_ioLDO_REG1w@w@ 5vcc18_flashLDO_REG22Z2Z5vcca_33LDO_REG3B@B@5vdd_10LDO_REG42Z2Z5avdd_33LDO_REG5w@2Z 5vccio_sdLDO_REG6B@B@ 5vdd10_lcdLDO_REG7w@w@5vcc_18LDO_REG8w@w@ 5vcc18_lcdSWITCH_REG15vcc_sdSWITCH_REG2 5vcc33_lcdi2c@ff660000(rockchip,rk3368-i2crockchip,rk3288-i2cf =+i2c Mdefault3okayaccelerometer@18 bosch,bma250 4pwm@ff680000(rockchip,rk3368-pwmrockchip,rk3288-pwmhDdefault5 _pwm disabledpwm@ff680010(rockchip,rk3368-pwmrockchip,rk3288-pwmhDdefault6 _pwm disabledpwm@ff680020(rockchip,rk3368-pwmrockchip,rk3288-pwmh D _pwm disabledpwm@ff680030(rockchip,rk3368-pwmrockchip,rk3288-pwmh0Ddefault7 _pwm disabledserial@ff690000&rockchip,rk3368-uartsnps,dw-apb-uarti O Wbaudclkapb_pclk 9default8 disabledmbox@ff6b0000rockchip,rk3368-mailboxk0 E pclk_mailboxO disabledsyscon@ff738000)rockchip,rk3368-pmugrfsysconsimple-mfds;;io-domains&rockchip,rk3368-pmu-io-voltage-domain disabledreboot-modesyscon-reboot-mode[bRBnRB|RB RBclock-controller@ff760000rockchip,rk3368-cruv-\  syscon@ff770000&rockchip,rk3368-grfsysconsimple-mfdw--io-domains"rockchip,rk3368-io-voltage-domain disabledwatchdog@ff800000 rockchip,rk3368-wdtsnps,dw-wdt p Ookaytimer@ff810000,rockchip,rk3368-timerrockchip,rk3288-timer  Bi2s-2ch@ff890000(rockchip,rk3368-i2srockchip,rk3066-i2s (i2s_clki2s_hclk T 99txrx disabledi2s-8ch@ff898000(rockchip,rk3368-i2srockchip,rk3066-i2s 5i2s_clki2s_hclk R 99txrxdefault: disabledinterrupt-controller@ffb71000 arm,gic-400@ @ `   pinctrlrockchip,rk3368-pinctrl-;+gpio0@ff750000rockchip,gpio-banku @ Q//gpio1@ff780000rockchip,gpio-bankx A Rgpio2@ff790000rockchip,gpio-banky B S44gpio3@ff7a0000rockchip,gpio-bankz C T##pcfg-pull-up==pcfg-pull-downpcfg-pull-none<<pcfg-pull-none-12ma, >>emmcemmc-clk;<emmc-cmd;=emmc-pwr;=emmc-bus1;=emmc-bus4@;====emmc-bus8;========gmacrgmii-pins;<<<> > >>> ><<<<<<rmii-pins;<<<> > ><<<<i2c0i2c0-xfer ;<<..i2c1i2c1-xfer ;<<33i2c2i2c2-xfer ; <<""i2c3i2c3-xfer ;<<$$i2c4i2c4-xfer ;<<%%i2c5i2c5-xfer ;<<&&i2si2s-8ch-bus; < <<<<<<<<::pwm0pwm0-pin;<55pwm1pwm1-pin;<66pwm3pwm3-pin;<77sdio0sdio0-bus1;=sdio0-bus4@;====sdio0-cmd;=sdio0-clk;<sdio0-cd;=sdio0-wp;=sdio0-pwr;=sdio0-bkpwr;=sdio0-int;=sdmmcsdmmc-clk; <  sdmmc-cmd; =  sdmmc-cd; =sdmmc-bus1;=sdmmc-bus4@;====  spi0spi0-clk;=spi0-cs0;=spi0-cs1;=spi0-tx;=spi0-rx;=spi1spi1-clk;=spi1-cs0;=spi1-cs1;=spi1-rx;=spi1-tx;=spi2spi2-clk; =spi2-cs0; =!!spi2-rx; =  spi2-tx; =tsadcotp-gpio;<++otp-out;<,,uart0uart0-xfer ;=<uart0-cts;<uart0-rts;<uart1uart1-xfer ;=<uart1-cts;<uart1-rts;<uart2uart2-xfer ;=<88uart3uart3-xfer ;=<uart3-cts;<uart3-rts;<uart4uart4-xfer ;=<uart4-cts;<uart4-rts;<keyspwr-key;<??pmicpmic-sleep;<11pmic-int;=00chosenIserial4:115200n8memory@0@memorygpio-keys gpio-keysdefault?power / UGPIO Power[tfvcc-sys-regulatorregulator-fixed5vcc_sysLK@LK@22 compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2cpudevice_typeregenable-method#cooling-cellslinux,phandlerangesinterrupts#dma-cellsarm,pl330-broken-no-flushpclocksclock-namesinterrupt-affinityclock-frequencyclock-output-names#clock-cellsmax-frequencyfifo-depthresetsreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delayno-emmcno-sdionum-slotssd-uhs-sdr12sd-uhs-sdr25pinctrl-namespinctrl-0rockchip,default-sample-phasevmmc-supplyvqmmc-supplydisable-wpkeep-power-in-suspendmmc-hs200-1_8vno-sdnon-removable#io-channel-cellspower-gpiostouchscreen-size-xtouchscreen-size-ysilead,max-fingersreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-name#pwm-cells#mbox-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsdmasdma-namesinterrupt-controller#interrupt-cellsrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsstdout-pathlabellinux,codewakeup-source