D8A(Aapm,mustangapm,xgene-storm +7APM X-Gene Mustang boardcpus+cpu@000=cpuapm,potenzaarm,armv8I Mspin-table[cpu@001=cpuapm,potenzaarm,armv8I Mspin-table[cpu@100=cpuapm,potenzaarm,armv8I Mspin-table[cpu@101=cpuapm,potenzaarm,armv8I Mspin-table[cpu@200=cpuapm,potenzaarm,armv8I Mspin-table[cpu@201=cpuapm,potenzaarm,armv8I Mspin-table[cpu@300=cpuapm,potenzaarm,armv8I Mspin-table[cpu@301=cpuapm,potenzaarm,armv8I Mspin-table[interrupt-controller@78010000arm,cortex-a15-gicl}@Ixxx x   timerarm,armv8-timer0 soc simple-bus+clocks+refclk fixed-clockrefclkpcppll@17000100apm,xgene-pcppll-clockpcppllIpcppllDsocpll@17000120apm,xgene-socpll-clocksocpllI socpllDsocplldiv2fixed-factor-clock socplldiv2  socplldiv2qmlclkapm,xgene-device-clockqmlclkIcsr-regqmlclkethclkapm,xgene-device-clockethclkIdiv-reg8. <ethclkmenetclkapm,xgene-device-clockIcsr-reg menetclksge0clk@1f21c000apm,xgene-device-clockI!csr-regJsge0clksge1clk@1f21c000apm,xgene-device-clockI!csr-regJ sge1clkxge0clk@1f61c000apm,xgene-device-clockIacsr-regJxge0clksataphy1clk@1f21c000apm,xgene-device-clockI!csr-reg sataphy1clk SdisabledZJessataphy1clk@1f22c000apm,xgene-device-clockI"csr-reg sataphy2clkSokZJ:essataphy1clk@1f23c000apm,xgene-device-clockI#csr-reg sataphy3clkSokZJ:essata01clk@1f21c000apm,xgene-device-clockI!csr-reg sata01clkZJes9sata23clk@1f22c000apm,xgene-device-clockI"csr-reg sata23clkZJes9sata45clk@1f23c000apm,xgene-device-clockI#csr-reg sata45clkZJes9rtcclk@17000000apm,xgene-device-clockI csr-regZ Jesrtcclkrngpkaclk@17000000apm,xgene-device-clockI csr-regZ Jes rngpkaclkpcie0clk@1f2bc000Sokapm,xgene-device-clockI+csr-reg pcie0clk  pcie1clk@1f2cc000 Sdisabledapm,xgene-device-clockI,csr-reg pcie1clk  pcie2clk@1f2dc000 Sdisabledapm,xgene-device-clockI-csr-reg pcie2clk  pcie3clk@1f50c000 Sdisabledapm,xgene-device-clockIPcsr-reg pcie3clkpcie4clk@1f51c000 Sdisabledapm,xgene-device-clockIQcsr-reg pcie4clkdmaclk@1f27c000apm,xgene-device-clockI'csr-regdmaclk  msi@79000000apm,xgene1-msiIy  csw@7e200000apm,xgene-cswsysconI~ mcba@7e700000apm,xgene-mcbsysconI~pmcbb@7e720000apm,xgene-mcbsysconI~refuse@1054a000apm,xgene-efusesysconIT   edac@78800000apm,xgene-edac+ Ix$ !'edacmc@7e800000apm,xgene-edac-mcI~edacmc@7e840000apm,xgene-edac-mcI~edacmc@7e880000apm,xgene-edac-mcI~edacmc@7e8c0000apm,xgene-edac-mcI~edacpmd@7c000000apm,xgene-edac-pmdI| edacpmd@7c200000apm,xgene-edac-pmdI| edacpmd@7c400000apm,xgene-edac-pmdI|@ edacpmd@7c600000apm,xgene-edac-pmdI|` pcie@1f2b0000Sok=pci$apm,xgene-storm-pcieapm,xgene-pciel+ I+csrcfgTC8BB  pcie@1f2c0000 Sdisabled=pci$apm,xgene-storm-pcieapm,xgene-pciel+ I,csrcfgTрC8BB  pcie@1f2d0000 Sdisabled=pci$apm,xgene-storm-pcieapm,xgene-pciel+ I-csrcfgTC8BB  pcie@1f500000 Sdisabled=pci$apm,xgene-storm-pcieapm,xgene-pciel+ IPcsrcfgTC8BB pcie@1f510000 Sdisabled=pci$apm,xgene-storm-pcieapm,xgene-pciel+ IQ csrcfgTC8BB serial@1c020000Sok=serial ns16550aI  Lreboot@17000014apm,xgene-rebootIserial@1c021000 Sdisabled=serial ns16550aI  Mserial@1c022000 Sdisabled=serial ns16550aI   Nserial@1c023000 Sdisabled=serial ns16550aI0  Ophy@1f21a000apm,xgene-phyI!" Sdisabled-?  phy@1f22a000apm,xgene-phyI""Sok-?  phy@1f23a000apm,xgene-phyI#"Sok-?  sata@1a000000apm,xgene-ahciPI!!!!p  SdisabledQ Vsata-physata@1a400000apm,xgene-ahciPI@""""p SokQ Vsata-physata@1a800000apm,xgene-ahci@I### SokQ Vsata-physbgpio@17001000apm,xgene-gpio-sbI`lH()*+,-rtc@10510000apm,xgene-rtcIQ Fethernet@17020000apm,xgene-enetSok0Ienet_csrring_csrring_cmd <|rgmiimdioapm,xgene-mdio+menetphy@3ethernet-phy-id001c.c915Iethernet@1f210000apm,xgene1-sgenetSok0I! enet_csrring_csrring_cmd|sgmiiethernet@1f210030apm,xgene1-sgenetSok0I!0 enet_csrring_csrring_cmd|sgmiiethernet@1f610000apm,xgene1-xgenetSok0Ia`enet_csrring_csrring_cmd`a|xgmiirng@10520000apm,xgene-rngIR Adma@1f270000apm,xgene-storm-dma=dma@I' @T< chosenmemory=memoryIgpio-keys gpio-keysbutton@1POWERt - compatibleinterrupt-parent#address-cells#size-cellsmodeldevice_typeregenable-methodcpu-release-addr#interrupt-cellsinterrupt-controllerinterruptslinux,phandleclock-frequencyrangesdma-ranges#clock-cellsclock-output-namesclocksclock-namesclock-multclock-divreg-namesdivider-offsetdivider-widthdivider-shiftcsr-maskstatuscsr-offsetenable-offsetenable-maskmsi-controllerregmap-cswregmap-mcbaregmap-mcbbregmap-efusememory-controllerpmd-controllerinterrupt-map-maskinterrupt-mapdma-coherentmsi-parentreg-shift#phy-cellsapm,tx-boost-gainapm,tx-eye-tuningphysphy-names#gpio-cellsgpio-controllerlocal-mac-addressphy-connection-typephy-handleport-idlabellinux,codelinux,input-type