Ð þíÊH¸(pà(hisilicon,hi6220-hikeyhisilicon,hi6220 +7HiKey Development Boardpsci arm,psci-0.2=smccpus+cpu-mapcluster0core0Dcore1Dcore2Dcore3Dcluster1core0Dcore1Dcore2Dcore3D cpu@0arm,cortex-a53arm,armv8HcpuTXpsciflcpu@1arm,cortex-a53arm,armv8HcpuTXpsciflcpu@2arm,cortex-a53arm,armv8HcpuTXpsciflcpu@3arm,cortex-a53arm,armv8HcpuTXpsciflcpu@100arm,cortex-a53arm,armv8HcpuTXpsciflcpu@101arm,cortex-a53arm,armv8HcpuTXpsciflcpu@102arm,cortex-a53arm,armv8HcpuTXpsciflcpu@103arm,cortex-a53arm,armv8HcpuTXpscif l interrupt-controller@f6801000 arm,gic-400@Tö€ö€ ö€@ ö€` t… š ÿfltimerarm,armv8-timer 0š ÿÿ ÿ ÿsoc simple-bus+¥ao_ctrl@f7800000hisilicon,hi6220-aoctrlsysconT÷€ ¬f l sys_ctrl@f7030000 hisilicon,hi6220-sysctrlsysconT÷ ¬¹f l media_ctrl@f4410000"hisilicon,hi6220-mediactrlsysconTôA¬pm_ctrl@f7032000hisilicon,hi6220-pmctrlsysconT÷ ¬uart@f8015000arm,pl011arm,primecellTøP š$Æ $ $Íuartclkapb_pclkuart@f7111000arm,pl011arm,primecellT÷ š%Æ  Íuartclkapb_pclk Ùdisableduart@f7112000arm,pl011arm,primecellT÷  š&Æ  Íuartclkapb_pclk Ùdisabled àLS-UART0uart@f7113000arm,pl011arm,primecellT÷0 š'Æ  Íuartclkapb_pclk àLS-UART1uart@f7114000arm,pl011arm,primecellT÷@ š(Æ  Íuartclkapb_pclk Ùdisabledaliasesæ/soc/uart@f8015000î/soc/uart@f7111000ö/soc/uart@f7112000þ/soc/uart@f7113000chosenserial3:115200n8memory@0HmemoryT@ compatibleinterrupt-parent#address-cells#size-cellsmodelmethodcpudevice_typeregenable-methodlinux,phandle#interrupt-cellsinterrupt-controllerinterruptsranges#clock-cells#reset-cellsclocksclock-namesstatuslabelserial0serial1serial2serial3stdout-path