T(8P(HPapm,mustangapm,xgene-storm +7APM X-Gene Mustang boardcpus+cpu@000=cpuapm,potenzaarm,armv8I Mspin-table[lcpu@001=cpuapm,potenzaarm,armv8I Mspin-table[lcpu@100=cpuapm,potenzaarm,armv8I Mspin-table[lcpu@101=cpuapm,potenzaarm,armv8I Mspin-table[lcpu@200=cpuapm,potenzaarm,armv8I Mspin-table[lcpu@201=cpuapm,potenzaarm,armv8I Mspin-table[lcpu@300=cpuapm,potenzaarm,armv8I Mspin-table[lcpu@301=cpuapm,potenzaarm,armv8I Mspin-table[ll2-cache-0cache}l2-cache-1cache}l2-cache-2cache}l2-cache-3cache}interrupt-controller@78010000arm,cortex-a15-gic@Ixxx x   }timerarm,armv8-timer0 pmu apm,potenza-pmuarm,armv8-pmuv3  soc simple-bus+clocks+refclk fixed-clockrefclk}pcppll@17000100apm,xgene-pcppll-clockpcppllIpcppllDsocpll@17000120apm,xgene-socpll-clocksocpllI socpllD}socplldiv2fixed-factor-clock socplldiv2 socplldiv2}ahbclk@17000000apm,xgene-device-clockI &div-reg0d?Mahbclk}sdioclk@1f2ac000apm,xgene-device-clock I* &csr-regdiv-reg[fo}0x?Msdioclk}qmlclkapm,xgene-device-clockqmlclkI&csr-regqmlclkethclkapm,xgene-device-clockethclkI&div-reg08? Methclk}  menetclkapm,xgene-device-clock I&csr-reg menetclk}##sge0clk@1f21c000apm,xgene-device-clockI!&csr-regfsge0clk}%%sge1clk@1f21c000apm,xgene-device-clockI!&csr-regf sge1clk}&&xge0clk@1f61c000apm,xgene-device-clockIa&csr-regfxge0clk}''xge1clk@1f62c000apm,xgene-device-clock disabledIb&csr-regfxge1clk}((sataphy1clk@1f21c000apm,xgene-device-clockI!&csr-reg sataphy1clk disabled[fo}}sataphy1clk@1f22c000apm,xgene-device-clockI"&csr-reg sataphy2clkok[f:o}}sataphy1clk@1f23c000apm,xgene-device-clockI#&csr-reg sataphy3clkok[f:o}}sata01clk@1f21c000apm,xgene-device-clockI!&csr-reg sata01clk[fo}9}sata23clk@1f22c000apm,xgene-device-clockI"&csr-reg sata23clk[fo}9}sata45clk@1f23c000apm,xgene-device-clockI#&csr-reg sata45clk[fo}9}  rtcclk@17000000apm,xgene-device-clockI &csr-reg[ fo}rtcclk}""rngpkaclk@17000000apm,xgene-device-clockI &csr-reg[ fo} rngpkaclk}))pcie0clk@1f2bc000okapm,xgene-device-clockI+&csr-reg pcie0clk}pcie1clk@1f2cc000 disabledapm,xgene-device-clockI,&csr-reg pcie1clk}pcie2clk@1f2dc000 disabledapm,xgene-device-clockI-&csr-reg pcie2clk}pcie3clk@1f50c000 disabledapm,xgene-device-clockIP&csr-reg pcie3clk}pcie4clk@1f51c000 disabledapm,xgene-device-clockIQ&csr-reg pcie4clk}dmaclk@1f27c000apm,xgene-device-clockI'&csr-regdmaclk}**msi@79000000apm,xgene1-msiIy}system-clk-controller@17000000apm,xgene-scusysconI}  reboot@17000014syscon-reboot 8jcsw@7e200000apm,xgene-cswsysconI~ }  mcba@7e700000apm,xgene-mcbsysconI~p}  mcbb@7e720000apm,xgene-mcbsysconI~r}  efuse@1054a000apm,xgene-efusesysconIT }rb@7e000000apm,xgene-rbsysconI~}edac@78800000apm,xgene-edac+   Ix$ !'edacmc@7e800000apm,xgene-edac-mcI~edacmc@7e840000apm,xgene-edac-mcI~edacmc@7e880000apm,xgene-edac-mcI~edacmc@7e8c0000apm,xgene-edac-mcI~edacpmd@7c000000apm,xgene-edac-pmdI| edacpmd@7c200000apm,xgene-edac-pmdI| edacpmd@7c400000apm,xgene-edac-pmdI|@ edacpmd@7c600000apm,xgene-edac-pmdI|` edacl3@7e600000apm,xgene-edac-l3I~`edacsoc@7e930000apm,xgene-edac-soc-v1I~pcie@1f2b0000ok=pci$apm,xgene-storm-pcieapm,xgene-pcie+ I+&csrcfgTC8BB"/pcie@1f2c0000 disabled=pci$apm,xgene-storm-pcieapm,xgene-pcie+ I,&csrcfgTрC8BB"/pcie@1f2d0000 disabled=pci$apm,xgene-storm-pcieapm,xgene-pcie+ I-&csrcfgTC8BB"/pcie@1f500000 disabled=pci$apm,xgene-storm-pcieapm,xgene-pcie+ IP&csrcfgTC8BB"/pcie@1f510000 disabled=pci$apm,xgene-storm-pcieapm,xgene-pcie+ IQ &csrcfgTC8BB"/mailbox@10540000apm,xgene-slimpro-mboxIT:`}i2cslimproapm,xgene-slimpro-i2cFserial@1c020000ok=serial ns16550aIM  Lserial@1c021000 disabled=serial ns16550aIM  Mserial@1c022000 disabled=serial ns16550aI M  Nserial@1c023000 disabled=serial ns16550aI0M  Ommc@1c000000arasan,sdhci-4.9aI I"Wclk_xinclk_ahbokgpio0@1701c000apm,xgene-gpioI@`pgpio@1c024000snps,dw-apb-gpioI@|+gpio-controller@0snps,dw-apb-gpio-port` Ii2c@10512000 disabled+snps,designware-i2cIQ  Dphy@1f21a000apm,xgene-phyI! disabled  }phy@1f22a000apm,xgene-phyI"ok  }phy@1f23a000apm,xgene-phyI#ok  }!!sata@1a000000apm,xgene-ahciPI!!!!p " disabled sata-physata@1a400000apm,xgene-ahciPI@""""p "ok sata-physata@1a800000apm,xgene-ahci@I### "ok ! sata-phydwusb@19000000 disabled snps,dwc3I "hostdwusb@19800000 disabled snps,dwc3I "hostgpio@17001000apm,xgene-gpio-sbIp`H()*+,- }++rtc@10510000apm,xgene-rtcIQ F"ethernet@17020000apm,xgene-enetok0I&enet_csrring_csrring_cmd <"#rgmii $mdioapm,xgene-mdio+menetphy@3ethernet-phy-id001c.c915I}$$ethernet@1f210000apm,xgene1-sgenetok0I! &enet_csrring_csrring_cmd"%sgmiiethernet@1f210030apm,xgene1-sgenetok0I!0 &enet_csrring_csrring_cmd"&sgmiiethernet@1f610000apm,xgene1-xgenetok0Ia`&enet_csrring_csrring_cmd``abcdefg"'xgmiiethernet@1f620000apm,xgene1-xgenet disabled0Ib`&enet_csrring_csrring_cmdlm"(xgmiirng@10520000apm,xgene-rngIR A)dma@1f270000apm,xgene-storm-dma=dma@I' @T<"*chosenmemory=memoryIgpio-keys gpio-keysbutton@1&POWER,t7 +poweroff_mbox@10548000sysconIT0},,poweroff@10548010syscon-poweroff,8j compatibleinterrupt-parent#address-cells#size-cellsmodeldevice_typeregenable-methodcpu-release-addrnext-level-cachelinux,phandle#interrupt-cellsinterrupt-controllerinterruptsclock-frequencyrangesdma-ranges#clock-cellsclock-output-namesclocksclock-namesclock-multclock-divreg-namesdivider-offsetdivider-widthdivider-shiftcsr-offsetcsr-maskenable-offsetenable-maskstatusmsi-controllerregmapregmap-cswregmap-mcbaregmap-mcbbregmap-efuseregmap-rbmemory-controllerpmd-controllerinterrupt-map-maskinterrupt-mapdma-coherentmsi-parent#mbox-cellsmboxesreg-shiftno-1-8-vgpio-controller#gpio-cellsreg-io-widthsnps,nr-gpiosbus_num#phy-cellsapm,tx-boost-gainapm,tx-eye-tuningphysphy-namesdr_modelocal-mac-addressphy-connection-typephy-handleport-idchannellabellinux,codelinux,input-type