8(+hisilicon,hip06-d03 +&7Hisilicon Hip06 D03 Development Boardpsci arm,psci-0.2=smccpus+cpu-mapcluster0core0Dcore1Dcore2Dcore3Dcluster1core0Dcore1Dcore2Dcore3D cluster2core0D core1D core2D core3D cluster3core0Dcore1Dcore2Dcore3Dcpu@10000Hcpuarm,cortex-a57arm,armv8TXpscifw}cpu@10001Hcpuarm,cortex-a57arm,armv8TXpscifw}cpu@10002Hcpuarm,cortex-a57arm,armv8TXpscifw}cpu@10003Hcpuarm,cortex-a57arm,armv8TXpscifw}cpu@10100Hcpuarm,cortex-a57arm,armv8TXpscifw}cpu@10101Hcpuarm,cortex-a57arm,armv8TXpscifw}cpu@10102Hcpuarm,cortex-a57arm,armv8TXpscifw}cpu@10103Hcpuarm,cortex-a57arm,armv8TXpscifw } cpu@10200Hcpuarm,cortex-a57arm,armv8TXpscifw } cpu@10201Hcpuarm,cortex-a57arm,armv8TXpscifw } cpu@10202Hcpuarm,cortex-a57arm,armv8TXpscifw } cpu@10203Hcpuarm,cortex-a57arm,armv8TXpscifw } cpu@10300Hcpuarm,cortex-a57arm,armv8TXpscifw}cpu@10301Hcpuarm,cortex-a57arm,armv8TXpscifw}cpu@10302Hcpuarm,cortex-a57arm,armv8TXpscifw}cpu@10303Hcpuarm,cortex-a57arm,armv8TXpscifw}l2-cache0cachew}l2-cache1cachew}l2-cache2cachew}l2-cache3cachew}interrupt-controller@4d000000 arm,gic-v3+PTMM0  w}interrupt-controller@c6000000arm,gic-v3-itsTw}timerarm,armv8-timer0   pmuarm,cortex-a57-pmu mbigen_pcie@a0080000hisilicon,mbigen-v2Tintc_usbw}soc simple-bus+ohci@a7030000 generic-ohciT @$okehci@a7020000 generic-ehciT A$okmemory@00000000HmemoryT@chosen compatibleinterrupt-parent#address-cells#size-cellsmodelmethodcpudevice_typeregenable-methodnext-level-cachelinux,phandle#interrupt-cellsrangesinterrupt-controller#redistributor-regionsredistributor-strideinterruptsmsi-controller#msi-cellsmsi-parentnum-pinsdma-coherentstatus