sG8l({l(hisilicon,hi6220-hikeyhisilicon,hi6220 +7HiKey Development Boardpsci arm,psci-0.2=smccpus+cpu-mapcluster0core0Dcore1Dcore2Dcore3Dcluster1core0Dcore1Dcore2Dcore3D idle-statesHpscicpu-sleeparm,idle-stateUf}  cluster-sleeparm,idle-stateUf} cpu@0arm,cortex-a53arm,armv8cpupsci   +=L \7cpu@1arm,cortex-a53arm,armv8cpupsci  L cpu@2arm,cortex-a53arm,armv8cpupsci  L cpu@3arm,cortex-a53arm,armv8cpupsci  L cpu@100arm,cortex-a53arm,armv8cpupsci L cpu@101arm,cortex-a53arm,armv8cpupsci L cpu@102arm,cortex-a53arm,armv8cpupsci L cpu@103arm,cortex-a53arm,armv8cpupsci L   l2-cache0cache  l2-cache1cachecpu_opp_tableoperating-points-v2v  opp00 eހ opp01ހ opp02+s@ opp0398p` opp04GKP interrupt-controller@f6801000 arm,gic-400@ @ `   timerarm,armv8-timer 0   soc simple-bus+sram@fff80000!hisilicon,hi6220-sramctrlsyscon ao_ctrl@f7800000hisilicon,hi6220-aoctrlsyscon sys_ctrl@f7030000 hisilicon,hi6220-sysctrlsyscon media_ctrl@f4410000"hisilicon,hi6220-mediactrlsysconApm_ctrl@f7032000hisilicon,hi6220-pmctrlsyscon stub_clockhisilicon,hi6220-stub-clkmbox-tx   uart@f8015000arm,pl011arm,primecellP $$$%uartclkapb_pclkuart@f7111000arm,pl011arm,primecell %%uartclkapb_pclk1default ?Iokuart@f7112000arm,pl011arm,primecell  &%uartclkapb_pclk1default?Iok PLS-UART0uart@f7113000arm,pl011arm,primecell0 '%uartclkapb_pclk1default?Iok PLS-UART1uart@f7114000arm,pl011arm,primecell@ (%uartclkapb_pclk1default? Idisabledtimer@f8008000arm,sp804arm,primecell%timer1timer2apb_pclkrtc@f8003000arm,pl031arm,primecell0  % %apb_pclkrtc@f8004000arm,pl031arm,primecell@ & %apb_pclkpinmux@f7010000pinctrl-single|+Vh pPX`hpx!+08Jz~1default? !"))gpio-rangeboot_sel_pmx_funcemmc_pmx_funcP  $77sd_pmx_func0  >>sd_pmx_idle0  AAsdio_pmx_func0(,048<DDsdio_pmx_idle0(,048<GGisp_pmx_func$(,048<@DHLPTX\`hkadc_ssi_pmx_funchcodec_clk_pmx_funcl  codec_pmx_func ptx|fm_pmx_func bt_pmx_func pwm_in_pmx_func!!bl_pwm_pmx_func""uart0_pmx_funcuart1_pmx_func uart2_pmx_func uart3_pmx_func uart4_pmx_func uart5_pmx_funci2c0_pmx_func--i2c1_pmx_func//i2c2_pmx_func11spi0_pmx_func **pinmux@f7010800pinconf-single+h 1default?#$%&'boot_sel_cfg_func*p##hkadc_ssi_cfg_funcl*p$$emmc_clk_cfg_func* p88emmc_cfg_funcH  $(*p99emmc_rst_cfg_func,*p::sd_clk_cfg_func *0p??sd_clk_cfg_idle *pBBsd_cfg_func( * p@@sd_cfg_idle( *pCCsdio_clk_cfg_func4* pEEsdio_clk_cfg_idle4*pHHsdio_cfg_func(8<@DH*pFFsdio_cfg_idle(8<@DH*pIIisp_cfg_func1x(,048<@DHLPX\`d*pisp_cfg_idle148*pisp_cfg_func2T*pcodec_clk_cfg_funcp*p%%codec_clk_cfg_idlep*pcodec_cfg_func1t*pcodec_cfg_func2x|*pcodec_cfg_idle2x|*pfm_cfg_func *pbt_cfg_func *pbt_cfg_idle *ppwm_in_cfg_func*p&&bl_pwm_cfg_func*p''uart0_cfg_func1*puart0_cfg_func2*puart1_cfg_func1*puart1_cfg_func2*puart2_cfg_func *puart3_cfg_func *puart4_cfg_func *puart5_cfg_func*pi2c0_cfg_func*p..i2c1_cfg_func*p00i2c2_cfg_func*p22spi0_cfg_func *p++pinmux@f8001800pinconf-singlex+h 1default?(rstout_n_cfg_func*p((pmu_peri_en_cfg_func*psysclk0_en_cfg_func*pjtag_tdo_cfg_func * prf_reset_cfg_funcpt*pgpio@f8011000arm,pl061arm,primecell 4HX %apb_pclkOdPWR_HOLDDSI_SELUSB_HUB_RESET_NUSB_SELHDMI_PDWL_REG_ONPWRON_DET5V_HUB_EN33gpio@f8012000arm,pl061arm,primecell  5HX %apb_pclk:dSD_DETHDMI_INTPMU_IRQ_NWL_HOST_WAKENCNCNCBT_REG_ON==gpio@f8013000arm,pl061arm,primecell0 6HX %apb_pclkBdGPIO-AGPIO-BGPIO-CGPIO-DGPIO-EUSB_ID_DETUSB_VBUS_DETGPIO-Hgpio@f8014000arm,pl061arm,primecell@ 7HXt)P %apb_pclk%dGPIO3_0NCNCNCWLAN_ACTIVENCNCNNgpio@f7020000arm,pl061arm,primecell 8HXt)X %apb_pclk?dUSER_LED1USER_LED2USER_LED3USER_LED4SD_SELNCNCBT_ACTIVEMMgpio@f7021000arm,pl061arm,primecell 9HXt)` %apb_pclk?dNCNC[UART1_RxD][UART1_TxD][AUX_SSI1]NC[PCM_CLK][PCM_FS]gpio@f7022000arm,pl061arm,primecell  :HXt)h %apb_pclk=d[SPI0_DIN][SPI0_DOUT][SPI0_CS][SPI0_SCLK]NCNCNCGPIO-G,,gpio@f7023000arm,pl061arm,primecell0 ;HXt)p %apb_pclk$dNCNCNCNC[PCM_DI][PCM_DO]NCNCgpio@f7024000arm,pl061arm,primecell@ <HX t)x) %apb_pclkdNC[CEC_CLK_19_2MHZ]NCgpio@f7025000arm,pl061arm,primecellP =HXt) %apb_pclk'dGPIO-JGPIO-LNCNCNCNC[ISP_CCLK0]gpio@f7026000arm,pl061arm,primecell` >HX t)) %apb_pclk?dBOOT_SEL[ISP_CCLK1]GPIO-IGPIO-KNCNC[I2C2_SDA][I2C2_SCL]gpio@f7027000arm,pl061arm,primecellp ?HX t)) %apb_pclk"d[I2C3_SDA][I2C3_SCL]NCNCNCgpio@f7028000arm,pl061arm,primecell @HX t)!)+ %apb_pclk8d[BT_PCM_XFS][BT_PCM_DI][BT_PCM_DO]NCNCNCNCGPIO-Fgpio@f7029000arm,pl061arm,primecell AHXt)0 %apb_pclkhd[UART0_RX][UART0_TX][BT_UART1_CTS][BT_UART1_RTS][BT_UART1_RX][BT_UART1_TX][UART0_CTS][UART0_RTS]gpio@f702a000arm,pl061arm,primecell BHXt)8 %apb_pclkZd[UART0_RxD][UART0_TxD][I2C0_SCL][I2C0_SDA][I2C1_SCL][I2C1_SDA][I2C2_SCL][I2C2_SDA]gpio@f702b000arm,pl061arm,primecell CHX0t)J)z)~ %apb_pclk dNCgpio@f702c000arm,pl061arm,primecell DHXt) %apb_pclkgpio@f702d000arm,pl061arm,primecell EHXt) %apb_pclkgpio@f702e000arm,pl061arm,primecell FHXt) %apb_pclkgpio@f702f000arm,pl061arm,primecell GHXt) %apb_pclkspi@f7106000arm,pl022arm,primecell` 2 %apb_pclk1default?*+ ,Ioki2c@f7100000snps,designware-i2c , ,1default?-.Ioki2c@f7101000snps,designware-i2c -,1default?/0Ioki2c@f7102000snps,designware-i2c  .,1default?12 Idisabledregulator@0regulator-fixed fixed_5v_hubLK@LK@ 3 44usbphyhisilicon,hi6220-usb-phy!,4755usb@f72c0000hisilicon,hi6220-usb,S5 Xusb2-phy%otgbotgjt Mmailbox@f7510000hisilicon,hi6220-mbox Q ^dwmmc0@f723d000hisilicon,hi6220-dw-mshc# H%ciubiu61default?789:dwmmc1@f723e000hisilicon,hi6220-dw-mshc7# I+%ciubiu;<  += 1defaultidle ?>?@ 4ABCdwmmc2@f723f000hisilicon,hi6220-dw-mshc# J%ciubiu> 1defaultidle ?DEF 4GHIHJ+wlcore@2 ti,wl1835 =tsensor@0,f7030700hisilicon,tsensor  %thermal_clkYKKthermal-zonescls0o}d Ktripstrip-point@0passivetrip-point@1$passiveLLcooling-mapsmap0L regulator@1regulator-fixedwlan-en-regulatorw@w@ 3pJJaliases/soc/uart@f8015000 /soc/uart@f7111000/soc/uart@f7112000/soc/uart@f7113000chosen$serial3:115200n8memory@0memory@`A6leds gpio-ledsuser_led4 Puser_led4 M 0heartbeatuser_led3 Puser_led3 M0mmc0user_led2 Puser_led2 M0mmc1user_led1 Puser_led1 M0cpu0wlan_active_led Pwifi_active N0phy0txFoffbt_active_led Pbt_active M0hci0rxFoffpmic@f8000000hisilicon,hi655x-pmic T=regulatorsLDO2 LDO2_2V8&%0_xLDO7 LDO7_SDIOw@2Z_x;;LDO10 LDO10_2V85w@-_h<<LDO13 LDO13_1V8j0_xLDO14 LDO14_2V8&%0_xLDO15 LDO15_1V8j0 _xLDO17 LDO17_2V5&%0_xLDO19 LDO19_3V0w@-_h66LDO21 LDO21_1V8-P _xLDO22 LDO22_1V2 O _x compatibleinterrupt-parent#address-cells#size-cellsmodelmethodcpuentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uslinux,phandlewakeup-latency-usdevice_typeregenable-methodnext-level-cacheclocksoperating-points-v2cooling-min-levelcooling-max-level#cooling-cellscpu-idle-statesdynamic-power-coefficientopp-sharedopp-hzopp-microvoltclock-latency-ns#interrupt-cellsinterrupt-controllerinterruptsranges#clock-cells#reset-cellshisilicon,hi6220-clk-srammbox-namesmboxesclock-namespinctrl-namespinctrl-0statuslabel#gpio-range-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,gpio-range#pinctrl-single,gpio-range-cellspinctrl-single,pinspinctrl-single,bias-pulldownpinctrl-single,bias-pulluppinctrl-single,drive-strengthgpio-controller#gpio-cellsgpio-line-namesgpio-rangesbus-idenable-dmanum-cscs-gpiosi2c-sda-hold-time-nsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-ongpioregulator-always-on#phy-cellsphy-supplyhisilicon,peripheral-sysconphysphy-namesdr_modeg-use-dmag-rx-fifo-sizeg-np-tx-fifo-sizeg-tx-fifo-size#mbox-cellsnum-slotscap-mmc-highspeednon-removablebus-widthvmmc-supplycard-detect-delaycap-sd-highspeedvqmmc-supplydisable-wpcd-gpiospinctrl-1broken-cdti,non-removable#thermal-sensor-cellspolling-delaypolling-delay-passivesustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicestartup-delay-usenable-active-highserial0serial1serial2serial3stdout-pathlinux,default-triggerdefault-statepmic-gpiosregulator-enable-ramp-delay