8`(d("nvidia,p2371-2180nvidia,tegra210 + 7NVIDIA Jetson TX1 Developer Kithost1x@50000000"nvidia,tegra210-host1xsimple-bus=P@AACLShost1x_fhost1x+rTTdpaux@54040000nvidia,tegra210-dpaux=T A L/ Sdpauxparent_fdpauxyokaypinmux-aux dpaux-ioaux  pinmux-i2c dpaux-ioi2c  pinmux-off dpaux-iooffi2c-bus+vi@54080000nvidia,tegra210-vi=T AE ydisabledtsec@54100000nvidia,tegra210-tsec=Tdc@54200000nvidia,tegra210-dc=T  AIL Sdcparent_fdcdc@54240000nvidia,tegra210-dc=T$ AJL Sdcparent_fdcdsi@54300000nvidia,tegra210-dsi=T0L0Sdsilpparent_0fdsiyokay+panel@0auo,b080uan01= vic@54340000nvidia,tegra210-vic=T4 ydisablednvjpg@54380000nvidia,tegra210-nvjpg=T8 ydisableddsi@54400000nvidia,tegra210-dsi=T@LRSdsilpparent_Rfdsi ydisabled+nvdec@54480000nvidia,tegra210-nvdec=TH ydisablednvenc@544c0000nvidia,tegra210-nvenc=TL ydisabledtsec@54500000nvidia,tegra210-tsec=TP ydisabledsor@54540000nvidia,tegra210-sor=TT AL L/Ssorparentdpsafe_fsor    auxi2coff ydisabledsor@54580000nvidia,tegra210-sor1=TX AK(L/Ssorsourceparentdpsafe_fsor   auxi2coffyokay+:IU hdpaux@545c0000nvidia,tegra124-dpaux=T\ AL/ Sdpauxparent_fdpaux ydisabledpinmux-aux dpaux-ioaux  pinmux-i2c dpaux-ioi2c  pinmux-off dpaux-iooff  i2c-bus+isp@54600000nvidia,tegra210-isp=T` AG ydisabledisp@54680000nvidia,tegra210-isp=Th AF ydisabledi2c@546c0000nvidia,tegra210-i2c-vi=Tl A ydisabledinterrupt-controller@50041000 arm,gic-400x@=PP P@ P`  A  gpu@57000000 nvidia,gm20b =WXAstallnonstallL+ Sgpupwrref_fgpu ydisabledinterrupt-controller@60004000nvidia,tegra210-ictlr`=`@@`A@`B@`C@`D@`E@x timer@60005000+nvidia,tegra210-timernvidia,tegra20-timer=`PHA)*yzLStimerclock@60006000nvidia,tegra210-car=``flow-controller@60007000nvidia,tegra210-flowctrl=`pgpio@6000d000>nvidia,tegra210-gpionvidia,tegra124-gpionvidia,tegra30-gpio=``A !"#7WY}xdma@60020000.nvidia,tegra210-apbdmanvidia,tegra148-apbdma=`AhijklmnopqrstuvwL"Sdma_"fdmaapbmisc@70000800/nvidia,tegra210-apbmiscnvidia,tegra20-apbmisc =pdpdpinmux@700008d4nvidia,tegra210-pinmux =pp0bootpinmuxpex_l0_rst_n_pa0pex_l0_rst_n_pa0pe0 ';Mpex_l0_clkreq_n_pa1pex_l0_clkreq_n_pa1pe0 ';Mpex_wake_n_pa2pex_wake_n_pa2pe ';Mpex_l1_rst_n_pa3pex_l1_rst_n_pa3pe1 ';Mpex_l1_clkreq_n_pa4pex_l1_clkreq_n_pa4pe1 ';Msata_led_active_pa5sata_led_active_pa5 ';pa6pa6sata ';dap1_fs_pb0 dap1_fs_pb0 ';dap1_din_pb1 dap1_din_pb1 ';dap1_dout_pb2dap1_dout_pb2 ';dap1_sclk_pb3dap1_sclk_pb3 ';spi2_mosi_pb4spi2_mosi_pb4spi2 ';spi2_miso_pb5spi2_miso_pb5spi2 ';spi2_sck_pb6 spi2_sck_pb6spi2 ';spi2_cs0_pb7 spi2_cs0_pb7spi2 ';spi1_mosi_pc0spi1_mosi_pc0 ';spi1_miso_pc1spi1_miso_pc1 ';spi1_sck_pc2 spi1_sck_pc2 ';spi1_cs0_pc3 spi1_cs0_pc3 ';spi1_cs1_pc4 spi1_cs1_pc4 ';spi4_sck_pc5 spi4_sck_pc5spi4 ';spi4_cs0_pc6 spi4_cs0_pc6spi4 ';spi4_mosi_pc7spi4_mosi_pc7spi4 ';spi4_miso_pd0spi4_miso_pd0spi4 ';uart3_tx_pd1 uart3_tx_pd1uartc ';uart3_rx_pd2 uart3_rx_pd2uartc ';uart3_rts_pd3uart3_rts_pd3uartc ';uart3_cts_pd4uart3_cts_pd4uartc ';dmic1_clk_pe0dmic1_clk_pe0i2s3 ';dmic1_dat_pe1dmic1_dat_pe1i2s3 ';dmic2_clk_pe2dmic2_clk_pe2i2s3 ';dmic2_dat_pe3dmic2_dat_pe3i2s3 ';dmic3_clk_pe4dmic3_clk_pe4 ';dmic3_dat_pe5dmic3_dat_pe5 ';pe6pe6 ';pe7pe7pwm3 ';gen3_i2c_scl_pf0gen3_i2c_scl_pf0i2c3 ';Mgen3_i2c_sda_pf1gen3_i2c_sda_pf1i2c3 ';Muart2_tx_pg0 uart2_tx_pg0uartb ';uart2_rx_pg1 uart2_rx_pg1uartb ';uart2_rts_pg2uart2_rts_pg2uartb ';uart2_cts_pg3uart2_cts_pg3uartb ';wifi_en_ph0 wifi_en_ph0 ';wifi_rst_ph1 wifi_rst_ph1 ';wifi_wake_ap_ph2wifi_wake_ap_ph2 ';ap_wake_bt_ph3ap_wake_bt_ph3 ';bt_rst_ph4 bt_rst_ph4 ';bt_wake_ap_ph5bt_wake_ap_ph5 ';ph6ph6 ';ap_wake_nfc_ph7ap_wake_nfc_ph7 ';nfc_en_pi0 nfc_en_pi0 ';nfc_int_pi1 nfc_int_pi1 ';gps_en_pi2 gps_en_pi2 ';gps_rst_pi3 gps_rst_pi3rsvd0 ';uart4_tx_pi4 uart4_tx_pi4uartd ';uart4_rx_pi5 uart4_rx_pi5uartd ';uart4_rts_pi6uart4_rts_pi6uartd ';uart4_cts_pi7uart4_cts_pi7uartd ';gen1_i2c_sda_pj0gen1_i2c_sda_pj0i2c1 ';Mgen1_i2c_scl_pj1gen1_i2c_scl_pj1i2c1 ';Mgen2_i2c_scl_pj2gen2_i2c_scl_pj2i2c2 ';Mgen2_i2c_sda_pj3gen2_i2c_sda_pj3i2c2 ';Mdap4_fs_pj4 dap4_fs_pj4i2s4b ';dap4_din_pj5 dap4_din_pj5i2s4b ';dap4_dout_pj6dap4_dout_pj6i2s4b ';dap4_sclk_pj7dap4_sclk_pj7i2s4b ';pk0pk0i2s5b ';pk1pk1i2s5b ';pk2pk2i2s5b ';pk3pk3i2s5b ';pk4pk4 ';pk5pk5 ';pk6pk6 ';pk7pk7 ';pl0pl0rsvd0 ';pl1pl1 ';sdmmc1_clk_pm0sdmmc1_clk_pm0sdmmc1 ';sdmmc1_cmd_pm1sdmmc1_cmd_pm1sdmmc1 ';sdmmc1_dat3_pm2sdmmc1_dat3_pm2sdmmc1 ';sdmmc1_dat2_pm3sdmmc1_dat2_pm3sdmmc1 ';sdmmc1_dat1_pm4sdmmc1_dat1_pm4sdmmc1 ';sdmmc1_dat0_pm5sdmmc1_dat0_pm5sdmmc1 ';sdmmc3_clk_pp0sdmmc3_clk_pp0sdmmc3 ';sdmmc3_cmd_pp1sdmmc3_cmd_pp1sdmmc3 ';sdmmc3_dat3_pp2sdmmc3_dat3_pp2sdmmc3 ';sdmmc3_dat2_pp3sdmmc3_dat2_pp3sdmmc3 ';sdmmc3_dat1_pp4sdmmc3_dat1_pp4sdmmc3 ';sdmmc3_dat0_pp5sdmmc3_dat0_pp5sdmmc3 ';cam1_mclk_ps0cam1_mclk_ps0 extperiph3 ';cam2_mclk_ps1cam2_mclk_ps1 extperiph3 ';cam_i2c_scl_ps2cam_i2c_scl_ps2i2cvi ';Mcam_i2c_sda_ps3cam_i2c_sda_ps3i2cvi ';Mcam_rst_ps4 cam_rst_ps4 ';cam_af_en_ps5cam_af_en_ps5 ';cam_flash_en_ps6cam_flash_en_ps6 ';cam1_pwdn_ps7cam1_pwdn_ps7 ';cam2_pwdn_pt0cam2_pwdn_pt0 ';cam1_strobe_pt1cam1_strobe_pt1 ';uart1_tx_pu0 uart1_tx_pu0uarta ';uart1_rx_pu1 uart1_rx_pu1uarta ';uart1_rts_pu2uart1_rts_pu2 ';uart1_cts_pu3uart1_cts_pu3 ';lcd_bl_pwm_pv0lcd_bl_pwm_pv0pwm0 ';lcd_bl_en_pv1lcd_bl_en_pv1 ';lcd_rst_pv2 lcd_rst_pv2 ';lcd_gpio1_pv3lcd_gpio1_pv3 ';lcd_gpio2_pv4lcd_gpio2_pv4pwm1 ';ap_ready_pv5 ap_ready_pv5 ';touch_rst_pv6touch_rst_pv6 ';touch_clk_pv7touch_clk_pv7touch ';modem_wake_ap_px0modem_wake_ap_px0 ';touch_int_px1touch_int_px1 ';motion_int_px2motion_int_px2 ';als_prox_int_px3als_prox_int_px3 ';temp_alert_px4temp_alert_px4 ';button_power_on_px5button_power_on_px5 ';button_vol_up_px6button_vol_up_px6 ';button_vol_down_px7button_vol_down_px7 ';button_slide_sw_py0button_slide_sw_py0 ';button_home_py1button_home_py1 ';lcd_te_py2 lcd_te_py2 displaya ';pwr_i2c_scl_py3pwr_i2c_scl_py3i2cpmu ';Mpwr_i2c_sda_py4pwr_i2c_sda_py4i2cpmu ';Mclk_32k_out_py5clk_32k_out_py5soc ';pz0pz0 ';pz1pz1sdmmc1 ';pz2pz2 ';pz3pz3 ';pz4pz4sdmmc1 ';pz5pz5soc ';dap2_fs_paa0 dap2_fs_paa0i2s2 ';dap2_sclk_paa1dap2_sclk_paa1i2s2 ';dap2_din_paa2dap2_din_paa2i2s2 ';dap2_dout_paa3dap2_dout_paa3i2s2 ';aud_mclk_pbb0aud_mclk_pbb0 ';dvfs_pwm_pbb1dvfs_pwm_pbb1cldvfs ';dvfs_clk_pbb2dvfs_clk_pbb2 ';gpio_x1_aud_pbb3gpio_x1_aud_pbb3 ';gpio_x3_aud_pbb4gpio_x3_aud_pbb4rsvd0 ';hdmi_cec_pcc0hdmi_cec_pcc0cec ';Mhdmi_int_dp_hpd_pcc1hdmi_int_dp_hpd_pcc1 ';Mspdif_out_pcc2spdif_out_pcc2rsvd1 ';spdif_in_pcc3spdif_in_pcc3rsvd1 ';usb_vbus_en0_pcc4usb_vbus_en0_pcc4usb ';Musb_vbus_en1_pcc5usb_vbus_en1_pcc5usb ';Mdp_hpd0_pcc6 dp_hpd0_pcc6dp ';pcc7pcc7rsvd0 ';Mspi2_cs1_pdd0spi2_cs1_pdd0spi2 ';qspi_sck_pee0qspi_sck_pee0rsvd1 ';qspi_cs_n_pee1qspi_cs_n_pee1rsvd1 ';qspi_io0_pee2qspi_io0_pee2rsvd1 ';qspi_io1_pee3qspi_io1_pee3rsvd1 ';qspi_io2_pee4qspi_io2_pee4rsvd1 ';qspi_io3_pee5qspi_io3_pee5rsvd1 ';core_pwr_req core_pwr_reqcore ';cpu_pwr_req cpu_pwr_reqcpu ';pwr_int_n pwr_int_npmi ';clk_32k_in clk_32k_inclk ';jtag_rtck jtag_rtckjtag ';clk_reqclk_reqrsvd1 ';shutdown shutdown shutdown ';serial@70006000)nvidia,tegra210-uartnvidia,tegra20-uart=p`@Z A$LSserial_fserialdirxtxyokayserial@70006040)nvidia,tegra210-uartnvidia,tegra20-uart=p`@@Z A%LSserial_fseriald  irxtx ydisabledserial@70006200)nvidia,tegra210-uartnvidia,tegra20-uart=pb@Z A.L7Sserial_7fseriald  irxtx ydisabledserial@70006300)nvidia,tegra210-uartnvidia,tegra20-uart=pc@Z AZLASserial_Afserialdirxtx ydisabledpwm@7000a000'nvidia,tegra210-pwmnvidia,tegra20-pwm=psLSpwm_fpwmyokayi2c@7000c000(nvidia,tegra210-i2cnvidia,tegra114-i2c=p A&+L Sdiv-clk_ fi2cdirxtx ydisabledi2c@7000c400(nvidia,tegra210-i2cnvidia,tegra114-i2c=p AT+L6Sdiv-clk_6fi2cdirxtxyokay~gpio@74 ti,tca9539=t..backlight@2c ti,lp8557=,r rlp8557rom_14hÇrom_13hi2c@7000c500(nvidia,tegra210-i2cnvidia,tegra114-i2c=p A\+LCSdiv-clk_Cfi2cdirxtx ydisabledi2c@7000c700(nvidia,tegra210-i2cnvidia,tegra114-i2c=p Ax+LgSdiv-clk_gfi2cdirxtx   defaultidleyokay~i2c@7000d000(nvidia,tegra210-i2cnvidia,tegra114-i2c=p A5+L/Sdiv-clk_/fi2cdirxtxyokay~pmic@3cmaxim,max77620=< AVxdefault++pinmuxgpio0gpio0gpiogpio1gpio1fps-outgpio2_3 gpio2gpio3fps-out3gpio4gpio4 32k-out1gpio5_6_7gpio5gpio6gpio7gpiofpsfps0D[fps1D[fps2Dregulators|sd0VDD_SOC '\-klsd1VDD_DDR_1V1_PMIC-klsd2VDD_PRE_REG_1V35pp-klsd3VDD_1V8w@w@-klldo0 AVDD_SYS_1V2OO---ldo1 VDD_PEX_1V05-""ldo2 VDDIO_SDMMC2Z2Z>-&&ldo3 VDD_CAM_HV**2-ldo4VDD_RTC P P-ldo5 VDD_TS_HV2Z2Z>-ldo6 VDD_TS_1V8w@w@$-ldo7AVDD_1V05_PLL-ldo8AVDD_SATA_HDMI_DP_1V05-i2c@7000d100(nvidia,tegra210-i2cnvidia,tegra114-i2c=p A?+LSdiv-clk_fi2cdirxtx   defaultidle ydisabledspi@7000d400(nvidia,tegra210-spinvidia,tegra114-spi=p A;+L)Sspi_)fspidirxtx ydisabledspi@7000d600(nvidia,tegra210-spinvidia,tegra114-spi=p AR+L,Sspi_,fspidirxtx ydisabledspi@7000d800(nvidia,tegra210-spinvidia,tegra114-spi=p AS+L.Sspi_.fspidirxtx ydisabledspi@7000da00(nvidia,tegra210-spinvidia,tegra114-spi=p A]+LDSspi_Dfspidirxtx ydisabledrtc@7000e000'nvidia,tegra210-rtcnvidia,tegra20-rtc=p ALSrtcpmc@7000e400nvidia,tegra210-pmc=p L%Spclkclk32k_inBpowergatesaudLk_Z((xusbaLSxusb-ss_fxusb-ssZxusbbL! Sxusb-dev__ fxusb-devZxusbcLY Sxusb-host_Y fxusb-hostZfuse@7000f800nvidia,tegra210-efuse=pLSfuse_'ffusememory-controller@70019000nvidia,tegra210-mc=pL Smc AMnhda@70030000'nvidia,tegra210-hdanvidia,tegra30-hda=p AQL}oShdahda2hdmihda2codec_2x_}ofhdahda2hdmihda2codec_2x ydisabledusb@70090000nvidia,tegra210-xusb0=p p p {hcdfpciipfsA'(XLYj"xSxusb_hostxusb_host_srcxusb_falcon_srcxusb_ssxusb_ss_div2xusb_ss_srcxusb_hs_srcxusb_fs_srcpll_u_480mclk_mpll_e_Yfxusb_hostxusb_ssxusb_srcyokay !*usb2-0usb2-1usb2-2usb2-3usb3-0usb3-1"#""padctl@7009f000nvidia,tegra210-xusb-padctl=p _fpadctlyokaypadsusb2LStrkyokaylanesusb2-0yokay8xusbusb2-1yokay8xusbusb2-2yokay8xusbusb2-3yokay8xusbhsicLStrk ydisabledlaneshsic-0 ydisabled8hsic-1 ydisabled8pcieLSpll_fphyyokaylanespcie-0yokay8pcie-x1pcie-1yokay8pcie-x4pcie-2yokay8pcie-x4pcie-3yokay8pcie-x4pcie-4yokay8pcie-x4pcie-5yokay8usb3-ss!!pcie-6yokay8usb3-ss  sataLSpll_fphyyokaylanessata-0yokay8sataportsusb2-0yokayCotgusb2-1yokayH$Chostusb2-2yokayH%Chostusb2-3yokayChosthsic-0 ydisabledusb3-0yokayTusb3-1yokayTusb3-2 ydisabledusb3-3 ydisabledsdhci@700b0000,nvidia,tegra210-sdhcinvidia,tegra124-sdhci=p  ALSsdhci_fsdhciyokayjt }&'sdhci@700b0200,nvidia,tegra210-sdhcinvidia,tegra124-sdhci=p  AL Ssdhci_ fsdhci ydisabledsdhci@700b0400,nvidia,tegra210-sdhcinvidia,tegra124-sdhci=p  ALESsdhci_Efsdhci ydisabledsdhci@700b0600,nvidia,tegra210-sdhcinvidia,tegra124-sdhci=p  ALSsdhci_fsdhciyokayjmipi@700e3000nvidia,tegra210-mipi=p0L8 Smipi-calaconnect@702c0000nvidia,tegra210-aconnectLk Sapeapb2ape(+rp,p, ydisabledspi@70410000nvidia,tegra210-qspi=pA A +LSqspi_fqspidirxtx ydisabledusb@7d0000002nvidia,tegra210-ehcinvidia,tegra30-ehciusb-ehci=}@ AutmiLSusb_fusb) ydisabledusb-phy@7d000000/nvidia,tegra210-usb-phynvidia,tegra30-usb-phy =}@}@utmiLSregpll_uutmi-pads_fusbutmi-pads2H Zn  ydisabled))usb@7d0040002nvidia,tegra210-ehcinvidia,tegra30-ehciusb-ehci=}@@ AutmiL:Susb_:fusb* ydisabledusb-phy@7d004000/nvidia,tegra210-usb-phynvidia,tegra30-usb-phy =}@@}@utmiL:Sregpll_uutmi-pads_:fusbutmi-pads2H Zn  ydisabled**cpus+cpu@0cpuarm,cortex-a57=cpu@1cpuarm,cortex-a57=cpu@2cpuarm,cortex-a57=cpu@3cpuarm,cortex-a57=timerarm,armv8-timer0A    aliases/i2c@7000d000/pmic@3c/rtc@7000e000/serial@70006000chosenserial0:115200n8memorymemory=clocks simple-bus+clock@0 fixed-clock=~regulators simple-bus+regulator@0regulator-fixed= VDD_SYS_MUXLK@LK@,,regulator@1regulator-fixed= VDD_5V0_SYSLK@LK@ s+ ,regulator@2regulator-fixed= VDD_3V3_SYS2Z2Z s+ ,('##regulator@3regulator-fixed=VDD_5V0_IO_SYSLK@LK@regulator@4regulator-fixed= VDD_3V3_SD2Z2Z s #(''regulator@5regulator-fixed=AVDD_DSI_CSI_1V2OO-regulator@6regulator-fixed=VDD_DIS_3V3_LCD2Z2Z s. #regulator@7regulator-fixed=VDD_LCD_1V8_DISw@w@ s. regulator@8regulator-fixed=RTL_5VLK@LK@ s9 $$regulator@9regulator-fixed=  USB_VBUS_EN1LK@LK@ s %%regulator@10regulator-fixed=  VDD_HDMI_5V0LK@LK@ s.  gpio-keys gpio-keys Egpio-keyspowerEPower KtVvolume_down EVolume Down Krvolume_up EVolume Up Ks compatibleinterrupt-parent#address-cells#size-cellsmodelreginterruptsclocksclock-namesresetsreset-namesrangesstatusgroupsfunctionlinux,phandleiommusnvidia,headnvidia,mipi-calibrateavdd-dsi-csi-supplyenable-gpiospower-supplybacklightpinctrl-0pinctrl-1pinctrl-2pinctrl-namesavdd-io-supplyvdd-pll-supplyhdmi-supplynvidia,ddc-i2c-busnvidia,hpd-gpio#interrupt-cellsinterrupt-controllerinterrupt-names#clock-cells#reset-cells#gpio-cellsgpio-controller#dma-cellsnvidia,pinsnvidia,functionnvidia,pullnvidia,tristatenvidia,enable-inputnvidia,open-drainnvidia,io-hvreg-shiftdmasdma-names#pwm-cellsclock-frequencydev-ctrlinit-brtpwm-periodpwmspwm-namesrom-addrrom-valdrive-push-pullmaxim,active-fps-sourcemaxim,active-fps-power-up-slotmaxim,active-fps-power-down-slotdrive-open-drainmaxim,fps-event-sourcemaxim,suspend-fps-time-period-usin-ldo0-1-supplyin-ldo7-8-supplyin-sd3-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-enable-ramp-delayregulator-ramp-delaynvidia,invert-interrupt#power-domain-cells#iommu-cellsreg-namesnvidia,xusb-padctlphysphy-namesdvddio-pex-supplyhvddio-pex-supplyavdd-usb-supplyavdd-pll-utmip-supplyavdd-pll-uerefe-supplydvdd-usb-ss-pll-supplyhvdd-usb-ss-pll-e-supply#phy-cellsmodevbus-supplynvidia,usb2-companionbus-widthno-1-8-vcd-gpiosvqmmc-supplyvmmc-supplynon-removable#nvidia,mipi-calibrate-cellspower-domainsphy_typenvidia,phynvidia,hssync-start-delaynvidia,idle-wait-delaynvidia,elastic-limitnvidia,term-range-adjnvidia,xcvr-setupnvidia,xcvr-lsfslewnvidia,xcvr-lsrslewnvidia,hssquelch-levelnvidia,hsdiscon-levelnvidia,xcvr-hsslewnvidia,has-utmi-pad-registersdevice_typertc0rtc1serial0stdout-pathenable-active-highvin-supplyregulator-disable-ramp-delaylabellinux,codewakeup-source