.58+l(+4)Qualcomm Technologies, Inc. MSM 8996 MTP&2qcom,msm8996-mtpchosen=serial0memoryImemoryUcpus&cpu@0Icpu 2qcom,kryoUYpscigx~l2-cache2cachex~cpu@1Icpu 2qcom,kryoUYpscigx~cpu@100Icpu 2qcom,kryoUYpscigx~l2-cache2cachex~cpu@101Icpu 2qcom,kryoUYpscigx~cpu-mapcluster0core0core1cluster1core0core1thermal-zonescpu-thermal0tripstrip0$Ppassivetrip1 Pcriticalcpu-thermal1tripstrip0$Ppassivetrip1 Pcriticalcpu-thermal2tripstrip0$Ppassivetrip1 Pcriticalcpu-thermal3 tripstrip0$Ppassivetrip1 Pcriticaltimer2arm,armv8-timer0   clocksxo_board 2fixed-clock$  xo_boardsleep_clk 2fixed-clock  sleep_clkpsci 2arm,psci-1.0`smcsoc& 2simple-businterrupt-controller@9bc0000 2arm,gic-v3#4I`U    x~clock-controller@3000002qcom,gcc-msm8996uU0 x ~ spi@075750002qcom,spi-qup-v2.2.1UWP _ o m coreifacedefaultsleep  & disabledi2c@075b50002qcom,i2c-qup-v2.2.1U[P e  ifacecoredefaultsleep  & disabledthermal-sensor@4a80002qcom,msm8996-tsensUJ x~serial@75b0000%2qcom,msm-uartdm-v1.4qcom,msm-uartdmU[ r  coreifaceokayi2c@075b60002qcom,i2c-qup-v2.2.1U[` f  ifacecoredefaultsleep& disabledserial@75b1000%2qcom,msm-uartdm-v1.4qcom,msm-uartdmU[ s  coreiface disabledi2c@075770002qcom,i2c-qup-v2.2.1UWp a m v ifacecoredefaultsleep& disabledspi@075ba0002qcom,spi-qup-v2.2.1U[ k  coreifacedefaultsleep& disabledsdhci@74a4900 disabled2qcom,sdhci-msm-v4UJIJ@hc_memcore_mem}hc_irqpwr_irq ifacecore h gpinctrl@10100002qcom,msm8996-pinctrlU0  4#blsp1_spi0_defaultx ~ pinmux (blsp_spi11gpio0gpio1gpio3pinmux_cs(gpio1gpio2pinconf1gpio0gpio1gpio36 Epinconf_cs1gpio26ERblsp1_spi0_sleepx ~ pinmux(gpio1gpio0gpio1gpio2gpio3pinconf1gpio0gpio1gpio2gpio36^blsp1_i2c2_defaultx~pinmux (blsp_i2c31gpio47gpio48pinconf1gpio47gpio486Eblsp1_i2c2_sleepx~pinmux(gpio1gpio47gpio48pinconf1gpio47gpio486Eblsp2_i2c0x ~ pinmux (blsp_i2c71gpio55gpio56pinconf1gpio55gpio566Eblsp2_i2c0_sleepx ~ pinmux(gpio1gpio55gpio56pinconf1gpio55gpio566Eblsp2_uart1_2pinspinmux (blsp_uart8 1gpio4gpio5pinconf 1gpio4gpio56Eblsp2_uart1_2pins_sleeppinmux(gpio 1gpio4gpio5pinconf 1gpio4gpio56Eblsp2_uart1_4pinspinmux (blsp_uart81gpio4gpio5gpio6gpio7pinconf1gpio4gpio5gpio6gpio76Eblsp2_uart1_4pins_sleeppinmux(gpio1gpio4gpio5gpio6gpio7pinconf1gpio4gpiio5gpio6gpio76Eblsp2_i2c1x~pinmux (blsp_i2c8 1gpio6gpio7pinconf 1gpio6gpio76Eblsp2_i2c1_sleepx~pinmux(gpio 1gpio6gpio7pinconf 1gpio6gpio76Eblsp2_uart2_2pinspinmux (blsp_uart91gpio49gpio50pinconf1gpio49gpio506Eblsp2_uart2_2pins_sleeppinmux(gpio1gpio49gpio50pinconf1gpio49gpio506Eblsp2_uart2_4pinspinmux (blsp_uart91gpio49gpio50gpio51gpio52pinconf1gpio49gpio50gpio51gpio526Eblsp2_uart2_4pins_sleeppinmux(gpio1gpio49gpio50gpio51gpio52pinconf1gpio49gpio50gpio51gpio526Eblsp2_spi5_defaultx~pinmux (blsp_spi121gpio85gpio86gpio88pinmux_cs(gpio1gpio87pinconf1gpio85gpio86gpio886 Epinconf_cs1gpio876ERblsp2_spi5_sleepx~pinmux(gpio1gpio85gpio86gpio87gpio88pinconf1gpio85gpio86gpio87gpio886^sdc2_clk_onconfig 1sdc2_clkE6sdc2_clk_offconfig 1sdc2_clkE6sdc2_cmd_onconfig 1sdc2_cmdm6 sdc2_cmd_offconfig 1sdc2_cmdm6sdc2_data_onconfig 1sdc2_datam6 sdc2_data_offconfig 1sdc2_datam6timer@09840000&2arm,armv7-timer-memU $frame@9850000zU  frame@9870000z U  disabledframe@9880000z !U  disabledframe@9890000z "U  disabledframe@98a0000z #U  disabledframe@98b0000z $U  disabledframe@98c0000z %U  disabledqcom,spmi@400f0002qcom,spmi-pmic-arb(U@ !corechnlsobsrvrintrcnfg periph_irq F&4#clock-controller@8c00002qcom,mmcc-msm8996uU(  %1|0G:i98p1,@x~aliases/soc/serial@75b0000 modelinterrupt-parent#address-cells#size-cellscompatiblestdout-pathdevice_typeregenable-methodnext-level-cachelinux,phandlecache-levelcpupolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresisinterrupts#clock-cellsclock-frequencyclock-output-namesranges#interrupt-cellsinterrupt-controller#redistributor-regionsredistributor-stride#reset-cells#power-domain-cellsclocksclock-namespinctrl-namespinctrl-0pinctrl-1status#thermal-sensor-cellsreg-namesinterrupt-namesbus-widthgpio-controller#gpio-cellsfunctionpinsdrive-strengthbias-disableoutput-highbias-pull-downbias-pull-upframe-numberqcom,eeqcom,channelassigned-clocksassigned-clock-ratesserial0