"/H(/RTSM_VE_AEMv8A arm,rtsm_ve,aemv8aarm,vexpress"1chosenaliases8=/smb@08000000/motherboard/iofpga@3,00000000/uart@0900008E/smb@08000000/motherboard/iofpga@3,00000000/uart@0a00008M/smb@08000000/motherboard/iofpga@3,00000000/uart@0b00008U/smb@08000000/motherboard/iofpga@3,00000000/uart@0c0000cpus"1cpu@0]cpu arm,armv8i mspin-table{cpu@1]cpu arm,armv8i mspin-table{cpu@2]cpu arm,armv8i mspin-table{cpu@3]cpu arm,armv8i mspin-table{l2-cache0cachememory@80000000]memory iinterrupt-controller@2c001000%arm,cortex-a15-gicarm,cortex-a9-gic"@i,, ,@ ,`   timerarm,armv8-timer0   pmuarm,armv8-pmuv30<=>?smb@08000000 simple-bus"1x  ?            !!""##$$%%&&''(())**motherboardrs1arm,vexpress,v2m-p1simple-bus"1flash@0,00000000arm,vexpress-flashcfi-flashi'vram@2,00000000arm,vexpress-vram i  ethernet@2,02000000smsc,lan91c111 iclk24mhz fixed-clock2n6 ?v2m:clk24mhzrefclk1mhz fixed-clock2B@?v2m:refclk1mhzrefclk32khz fixed-clock2?v2m:refclk32khziofpga@3,00000000 simple-bus"1 sysreg@010000arm,vexpress-sysregiRbsysctl@020000arm,sp810arm,primecelli nurefclktimclkapb_pclk20?timerclken0timerclken1timerclken2timerclken3 aaci@040000arm,pl041arm,primecelli n uapb_pclkmmci@050000arm,pl180arm,primecelli   numclkapb_pclkkmi@060000arm,pl050arm,primecelli nuKMIREFCLKapb_pclkkmi@070000arm,pl050arm,primecelli nuKMIREFCLKapb_pclkuart@090000arm,pl011arm,primecelli nuuartclkapb_pclkuart@0a0000arm,pl011arm,primecelli nuuartclkapb_pclkuart@0b0000arm,pl011arm,primecelli nuuartclkapb_pclkuart@0c0000arm,pl011arm,primecelli nuuartclkapb_pclkwdt@0f0000arm,sp805arm,primecellinuwdogclkapb_pclktimer@110000arm,sp804arm,primecellinutimclken1timclken2apb_pclktimer@120000arm,sp804arm,primecellinutimclken1timclken2apb_pclkrtc@170000arm,pl031arm,primecellin uapb_pclkclcd@1f0000arm,pl111arm,primecelli combinedn uclcdclkapb_pclk portendpoint  -  panel panel-dpiportendpoint   panel-timing_GO[0hhrzvirtio_block@0130000 virtio,mmioi*v2m-3v3regulator-fixed3V32Z2Zmccarm,vexpress,config-busoscclk1arm,vexpress-osc $jep2 ?v2m:oscclk1  resetarm,vexpress-reset muxfpgaarm,vexpress-muxfpga shutdownarm,vexpress-shutdown rebootarm,vexpress-reboot dvimodearm,vexpress-dvimode  modelcompatibleinterrupt-parent#address-cells#size-cellsserial0serial1serial2serial3device_typeregenable-methodcpu-release-addrnext-level-cachelinux,phandle#interrupt-cellsinterrupt-controllerinterruptsclock-frequencyrangesinterrupt-map-maskinterrupt-maparm,v2m-memory-mapbank-width#clock-cellsclock-output-namesgpio-controller#gpio-cellsclocksclock-namesassigned-clocksassigned-clock-parentscd-gpioswp-gpiosmax-frequencyvmmc-supplyinterrupt-namesarm,pl11x,framebuffermemory-regionmax-memory-bandwidthremote-endpointarm,pl11x,tft-r0g0b0-padshactivehback-porchhfront-porchhsync-lenvactivevback-porchvfront-porchvsync-lenregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onarm,vexpress,config-bridgearm,vexpress-sysreg,funcfreq-range