{8tL(t(hisilicon,hi6220-hikeyhisilicon,hi6220 +7HiKey Development Boardpsci arm,psci-0.2=smccpus+cpu-mapcluster0core0Dcore1Dcore2Dcore3Dcluster1core0Dcore1Dcore2Dcore3D idle-statesHpscicpu-sleeparm,idle-stateUf}  cluster-sleeparm,idle-stateUf} cpu@0arm,cortex-a53arm,armv8cpupsci   +=L \7cpu@1arm,cortex-a53arm,armv8cpupsci  L cpu@2arm,cortex-a53arm,armv8cpupsci  L cpu@3arm,cortex-a53arm,armv8cpupsci  L cpu@100arm,cortex-a53arm,armv8cpupsci L cpu@101arm,cortex-a53arm,armv8cpupsci L cpu@102arm,cortex-a53arm,armv8cpupsci L cpu@103arm,cortex-a53arm,armv8cpupsci L   l2-cache0cache  l2-cache1cachecpu_opp_tableoperating-points-v2v  opp00 eހ opp01ހ opp02+s@ opp0398p` opp04GKP interrupt-controller@f6801000 arm,gic-400@ @ `   timerarm,armv8-timer 0   soc simple-bus+sram@fff80000!hisilicon,hi6220-sramctrlsyscon ao_ctrl@f7800000hisilicon,hi6220-aoctrlsyscon sys_ctrl@f7030000 hisilicon,hi6220-sysctrlsyscon media_ctrl@f4410000"hisilicon,hi6220-mediactrlsysconAOOpm_ctrl@f7032000hisilicon,hi6220-pmctrlsyscon medianoc_ade@f4520000sysconR@NNstub_clockhisilicon,hi6220-stub-clkmbox-tx   uart@f8015000arm,pl011arm,primecellP $$$%uartclkapb_pclkuart@f7111000arm,pl011arm,primecell %%uartclkapb_pclk1default ?IokP)`рuart@f7112000arm,pl011arm,primecell  &%uartclkapb_pclk1default?Iok uLS-UART0uart@f7113000arm,pl011arm,primecell0 '%uartclkapb_pclk1default?Iok uLS-UART1uart@f7114000arm,pl011arm,primecell@ (%uartclkapb_pclk1default? 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%apb_pclkBGPIO-AGPIO-BGPIO-CGPIO-DGPIO-EUSB_ID_DETUSB_VBUS_DETGPIO-Hgpio@f8014000arm,pl061arm,primecell@ 7m})P %apb_pclk%GPIO3_0NCNCNCWLAN_ACTIVENCNCTTgpio@f7020000arm,pl061arm,primecell 8m})X %apb_pclk?USER_LED1USER_LED2USER_LED3USER_LED4SD_SELNCNCBT_ACTIVESSgpio@f7021000arm,pl061arm,primecell 9m})` %apb_pclk?NCNC[UART1_RxD][UART1_TxD][AUX_SSI1]NC[PCM_CLK][PCM_FS]gpio@f7022000arm,pl061arm,primecell  :m})h %apb_pclk=[SPI0_DIN][SPI0_DOUT][SPI0_CS][SPI0_SCLK]NCNCNCGPIO-G,,gpio@f7023000arm,pl061arm,primecell0 ;m})p %apb_pclk$NCNCNCNC[PCM_DI][PCM_DO]NCNCgpio@f7024000arm,pl061arm,primecell@ <m} )x) %apb_pclkNC[CEC_CLK_19_2MHZ]NCgpio@f7025000arm,pl061arm,primecellP =m}) %apb_pclk'GPIO-JGPIO-LNCNCNCNC[ISP_CCLK0]gpio@f7026000arm,pl061arm,primecell` >m} )) %apb_pclk?BOOT_SEL[ISP_CCLK1]GPIO-IGPIO-KNCNC[I2C2_SDA][I2C2_SCL]gpio@f7027000arm,pl061arm,primecellp ?m} )) %apb_pclk"[I2C3_SDA][I2C3_SCL]NCNCNCgpio@f7028000arm,pl061arm,primecell @m} )!)+ %apb_pclk8[BT_PCM_XFS][BT_PCM_DI][BT_PCM_DO]NCNCNCNCGPIO-Fgpio@f7029000arm,pl061arm,primecell Am})0 %apb_pclkh[UART0_RX][UART0_TX][BT_UART1_CTS][BT_UART1_RTS][BT_UART1_RX][BT_UART1_TX][UART0_CTS][UART0_RTS]gpio@f702a000arm,pl061arm,primecell Bm})8 %apb_pclkZ[UART0_RxD][UART0_TxD][I2C0_SCL][I2C0_SDA][I2C1_SCL][I2C1_SDA][I2C2_SCL][I2C2_SDA]gpio@f702b000arm,pl061arm,primecell Cm}0)J)z)~ %apb_pclk NCgpio@f702c000arm,pl061arm,primecell Dm}) %apb_pclkgpio@f702d000arm,pl061arm,primecell Em}) %apb_pclkgpio@f702e000arm,pl061arm,primecell Fm}) %apb_pclkgpio@f702f000arm,pl061arm,primecell Gm}) %apb_pclkspi@f7106000arm,pl022arm,primecell` 2 %apb_pclk1default?*+ ,Ioki2c@f7100000snps,designware-i2c , ,1default?-.Ioki2c@f7101000snps,designware-i2c -,1default?/0Ioki2c@f7102000snps,designware-i2c  .,1default?12Iok+adv7533@39 adi,adv75339 3 4portendpoint5RRregulator@0regulator-fixed fixed_5v_hubLK@)LK@A 4S66usbphyhisilicon,hi6220-usb-phygr6}77usb@f72c0000hisilicon,hi6220-usb,7 usb2-phy%otgotg Mmailbox@f7510000hisilicon,hi6220-mbox Q ^dwmmc0@f723d000hisilicon,hi6220-dw-mshc# H%ciubiu 'reset3=81default?9:;<dwmmc1@f723e000hisilicon,hi6220-dw-mshcI}[ly# I+%ciubiu 'reset==>3 3 1defaultidle ??@A BCDdwmmc2@f723f000hisilicon,hi6220-dw-mshc# J%ciubiu 'reset3 1defaultidle ?EFG HIJ=K+wlcore@2 ti,wl1835 3tsensor@0,f7030700hisilicon,tsensor  %thermal_clkLLthermal-zonescls0d %Ltripstrip-point@05Apassivetrip-point@15$ApassiveMMcooling-mapsmap0LM Qade@f4100000hisilicon,hi6220-adex `ade_basejN O sOOO(%clk_ade_coreclk_codec_jpegclk_ade_pixPOO`u**IokportendpointPQQdsi@f4107800hisilicon,hi6220-dsixO%pclkIokports+port@0endpointQPPport@1endpoint@0R55regulator@1regulator-fixedwlan-en-regulatorw@)w@ 4pKKaliases/soc/uart@f8015000/soc/uart@f7111000/soc/uart@f7112000/soc/uart@f7113000chosenserial3:115200n8memory@0memory` `A"reserved-memory+ramoops@0x21f00000ramoops!linux,cmashared-dma-pool reboot-mode-syscon@5f01000sysconsimple-mfdreboot-modesyscon-reboot-mode#wfU/wfU?wfUleds gpio-ledsuser_led4 uuser_led4 S Mheartbeatuser_led3 uuser_led3 SMmmc0user_led2 uuser_led2 SMmmc1user_led1 uuser_led1 SMcpu0wlan_active_led uwifi_active TMphy0txcoffbt_active_led ubt_active SMhci0rxcoffpmic@f8000000hisilicon,hi655x-pmic q3regulatorsLDO2 LDO2_2V8&%)0|xLDO7 LDO7_SDIOw@)2Z|x==LDO10 LDO10_2V85w@)-|h>>LDO13 LDO13_1V8j)0|xLDO14 LDO14_2V8&%)0|xLDO15 LDO15_1V8j)0AS|xLDO17 LDO17_2V5&%)0|xLDO19 LDO19_3V0w@)-|h88LDO21 LDO21_1V8-P)S|xLDO22 LDO22_1V2 )OAS|x compatibleinterrupt-parent#address-cells#size-cellsmodelmethodcpuentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uslinux,phandlewakeup-latency-usdevice_typeregenable-methodnext-level-cacheclocksoperating-points-v2cooling-min-levelcooling-max-level#cooling-cellscpu-idle-statesdynamic-power-coefficientopp-sharedopp-hzopp-microvoltclock-latency-ns#interrupt-cellsinterrupt-controllerinterruptsranges#clock-cells#reset-cellshisilicon,hi6220-clk-srammbox-namesmboxesclock-namespinctrl-namespinctrl-0statusassigned-clocksassigned-clock-rateslabel#gpio-range-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,gpio-range#pinctrl-single,gpio-range-cellspinctrl-single,pinspinctrl-single,bias-pulldownpinctrl-single,bias-pulluppinctrl-single,drive-strengthgpio-controller#gpio-cellsgpio-line-namesgpio-rangesbus-idenable-dmanum-cscs-gpiosi2c-sda-hold-time-nspd-gpioadi,dsi-lanesremote-endpointregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onregulator-always-on#phy-cellsphy-supplyhisilicon,peripheral-sysconphysphy-namesdr_modeg-use-dmag-rx-fifo-sizeg-np-tx-fifo-sizeg-tx-fifo-size#mbox-cellsnum-slotscap-mmc-highspeednon-removableresetsreset-namesbus-widthvmmc-supplycard-detect-delaycap-sd-highspeedsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50vqmmc-supplydisable-wpcd-gpiospinctrl-1broken-cdti,non-removable#thermal-sensor-cellspolling-delaypolling-delay-passivesustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicereg-nameshisilicon,noc-syscondma-coherentstartup-delay-usenable-active-highserial0serial1serial2serial3stdout-pathrecord-sizeconsole-sizeftrace-sizereusablelinux,cma-defaultoffsetmode-normalmode-bootloadermode-recoverylinux,default-triggerdefault-statepmic-gpiosregulator-enable-ramp-delay