<8:p(l:8hisilicon,hip06-d03 +&7Hisilicon Hip06 D03 Development Boardpsci arm,psci-0.2=smccpus+cpu-mapcluster0core0Dcore1Dcore2Dcore3Dcluster1core0Dcore1Dcore2Dcore3D cluster2core0D core1D core2D core3D cluster3core0Dcore1Dcore2Dcore3Dcpu@10000Hcpuarm,cortex-a57arm,armv8TXpscifw}cpu@10001Hcpuarm,cortex-a57arm,armv8TXpscifw}cpu@10002Hcpuarm,cortex-a57arm,armv8TXpscifw}cpu@10003Hcpuarm,cortex-a57arm,armv8TXpscifw}cpu@10100Hcpuarm,cortex-a57arm,armv8TXpscifw}cpu@10101Hcpuarm,cortex-a57arm,armv8TXpscifw}cpu@10102Hcpuarm,cortex-a57arm,armv8TXpscifw}cpu@10103Hcpuarm,cortex-a57arm,armv8TXpscifw } cpu@10200Hcpuarm,cortex-a57arm,armv8TXpscifw } cpu@10201Hcpuarm,cortex-a57arm,armv8TXpscifw } cpu@10202Hcpuarm,cortex-a57arm,armv8TXpscifw } cpu@10203Hcpuarm,cortex-a57arm,armv8TXpscifw } cpu@10300Hcpuarm,cortex-a57arm,armv8TXpscifw}cpu@10301Hcpuarm,cortex-a57arm,armv8TXpscifw}cpu@10302Hcpuarm,cortex-a57arm,armv8TXpscifw}cpu@10303Hcpuarm,cortex-a57arm,armv8TXpscifw}l2-cache0cachew}l2-cache1cachew}l2-cache2cachew}l2-cache3cachew}interrupt-controller@4d000000 arm,gic-v3+PTMM0  w}interrupt-controller@c6000000arm,gic-v3-itsTw}timerarm,armv8-timer0   pmuarm,cortex-a57-pmu mbigen_pcie@a0080000hisilicon,mbigen-v2Tintc_usbw}intc_sas1w!}!intc_sas2@w"}"mbigen_dsa@c0080000hisilicon,mbigen-v2Tintc_dsaf0w}intc-sas0 w}soc simple-bus+ohci@a7030000 generic-ohciT $okehci@a7020000 generic-ehciT $oksub_ctrl_c@60000000hisilicon,peri-subctrlsysconT`w}dsa_subctrl@c0000000hisilicon,dsa-subctrlsysconTw}pcie_subctl@a0000000"hisilicon,pcie-sas-subctrlsysconTw } sds_ctrl@c2200000sysconT w}mdio@603c0000hisilicon,hns-mdioT`<+8 8SZ+ethernet-phy@0ethernet-phy-ieee802.3-c22Tw}ethernet-phy@1ethernet-phy-ieee802.3-c22Tw}dsa@c7000000+hisilicon,hns-dsaf-v2 96port-16rss T`>ppe-basedsaf-base HW @ABCDEFGHIJKLMNOPQRSTUVWX      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      !"#$%&'()*+,-./0123456789:;<=>?jsw}port@0T|fiberport@1T|fiberport@4T|copperport@5T|copperethernet@4hisilicon,hns-nic-v2$okethernet@5hisilicon,hns-nic-v2$okethernet@0hisilicon,hns-nic-v2$okethernet@1hisilicon,hns-nic-v2$oksas@c3000000hisilicon,hip06-sas-v2TP  `Z0,8?K @ABCDEFGHIKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~YZ[\]^_`abcdefghijklmnopqrstuvwx$oksas@a2000000hisilicon,hip06-sas-v2TP  U Z ,?K !@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_$oksas@a3000000hisilicon,hip06-sas-v2TP   Zp,?K  "     `abcdefghijklmnopqrstuvwxyz{|}~$okmemory@00000000HmemoryT@chosen compatibleinterrupt-parent#address-cells#size-cellsmodelmethodcpudevice_typeregenable-methodnext-level-cachelinux,phandle#interrupt-cellsrangesinterrupt-controller#redistributor-regionsredistributor-strideinterruptsmsi-controller#msi-cellsmsi-parentnum-pinsdma-coherentstatussubctrl-vbasemodereg-namessubctrl-sysconreset-field-offsetdesc-numbuf-sizeserdes-sysconport-rst-offsetport-mode-offsetmedia-typephy-handleae-handleport-idx-in-aelocal-mac-addresssas-addrhisilicon,sas-sysconctrl-reset-regctrl-reset-sts-regctrl-clock-ena-regqueue-countphy-counthip06-sas-v2-quirk-amt