Hd8D(DT -,amlogic,p212amlogic,s905xamlogic,meson-gxl17Amlogic Meson GXL (S905X) P212 Development Boardreserved-memory =hwrom@0DHsecmon@10000000D Hlinux,cma,shared-dma-poolOX ]@gcpus cpu@0ycpu,arm,cortex-a53arm,armv8Dpscicpu@1ycpu,arm,cortex-a53arm,armv8Dpscicpu@2ycpu,arm,cortex-a53arm,armv8Dpscicpu@3ycpu,arm,cortex-a53arm,armv8Dpscil2-cache0,cachearm-pmu,arm,cortex-a53-pmu0psci ,arm,psci-0.2smctimer,arm,armv8-timer0   xtal-clk ,fixed-clockn6xtal  firmwaresecure-monitor*,amlogic,meson-gx-smamlogic,meson-gxbb-smefuse0,amlogic,meson-gx-efuseamlogic,meson-gxbb-efuse sn@14Deth_mac@34D4bid@46DF0scpi),amlogic,meson-gxbb-scpiarm,scpi-pre-1.0 clocks,arm,scpi-clocksscpi_clocks@0,arm,scpi-dvfs-clocksvcpusensors,arm,scpi-sensors"soc ,simple-bus =cbus@c1100000 ,simple-busD =reset-controller@44040,amlogic,meson-gx-resetamlogic,meson-gxbb-resetDD 8""serial@84c0,amlogic,meson-uartD  EokayL Vdefaultdserial@84dc,amlogic,meson-uartD K  Edisabledi2c@8500,,amlogic,meson-gx-i2camlogic,meson-gxbb-i2cD    Edisabledpwm@8550,,amlogic,meson-gx-pwmamlogic,meson-gxbb-pwmDPt Edisabledpwm@8650,,amlogic,meson-gx-pwmamlogic,meson-gxbb-pwmDPt Edisabledadc@8680.,amlogic,meson-gxl-saradcamlogic,meson-saradcD4 IEokay$ Eab clkincoresanaadc_clkadc_selpwm@86c0,,amlogic,meson-gx-pwmamlogic,meson-gxbb-pwmDtEokayLVdefaultclkin0$$serial@8700,amlogic,meson-uartD ]  Edisabledi2c@87c0,,amlogic,meson-gx-i2camlogic,meson-gxbb-i2cD    Edisabledi2c@87e0,,amlogic,meson-gx-i2camlogic,meson-gxbb-i2cD    Edisabledspi@8c800,amlogic,meson-gx-spifcamlogic,meson-gxbb-spifcD  Edisabled"watchdog@98d0,,amlogic,meson-gx-wdtamlogic,meson-gxbb-wdtD interrupt-controller@c4301000 ,arm,gic-400@D00 0@ 0`   sram@c80000008,amlogic,meson-gx-sramamlogic,meson-gxbb-srammmio-sramD@ =@scp-shmem@08,amlogic,meson-gx-scp-shmemamlogic,meson-gxbb-scp-shmemD0  scp-shmem@2008,amlogic,meson-gx-scp-shmemamlogic,meson-gxbb-scp-shmemD4  aobus@c8100000 ,simple-busD =clock-controller@040&,amlogic,gx-aoclkcamlogic,gxbb-aoclkcD@8serial@4c0,amlogic,meson-uartD  EokayLVdefaultserial@4e0,amlogic,meson-uartD   Edisabledi2c@500,,amlogic,meson-gx-i2camlogic,meson-gxbb-i2cD    Edisabled]pwm@550,,amlogic,meson-gx-pwmamlogic,meson-gxbb-pwmDPt Edisabledir@580*,amlogic,meson-gx-iramlogic,meson-gxbb-irD@ EokayLVdefaultpinctrl@14 ,amlogic,meson-gxl-aobus-pinctrl =bank@140D,$muxpullgpiouart_ao_amuxuart_tx_ao_auart_rx_ao_auart_aouart_ao_a_cts_rtsmuxuart_cts_ao_auart_rts_ao_auart_aouart_ao_bmuxuart_tx_ao_buart_rx_ao_b uart_ao_buart_ao_b_0_1muxuart_tx_ao_b_0uart_rx_ao_b_1 uart_ao_buart_ao_b_cts_rtsmuxuart_cts_ao_buart_rts_ao_b uart_ao_bremote_input_aomuxremote_input_aoremote_input_aoi2c_aomuxi2c_sck_aoi2c_sda_aoi2c_aopwm_ao_a_3mux pwm_ao_a_3 pwm_ao_apwm_ao_a_8mux pwm_ao_a_8 pwm_ao_apwm_ao_bmux pwm_ao_b pwm_ao_bpwm_ao_b_6mux pwm_ao_b_6 pwm_ao_bi2s_out_ch23_aomuxi2s_out_ch23_ao i2s_out_aoi2s_out_ch45_aomuxi2s_out_ch45_ao i2s_out_aospdif_out_ao_6muxspdif_out_ao_6 spdif_out_aospdif_out_ao_9muxspdif_out_ao_9 spdif_out_aoperiphs@c8834000 ,simple-busDȃ@  =ȃ@ rng,amlogic,meson-rngDpinctrl@4b0",amlogic,meson-gxl-periphs-pinctrl =bank@4b0@D( 0@muxpullpull-enablegpioeemmcmux(emmc_nand_d07emmc_cmdemmc_clkemmc_dsemmcnormuxnor_dnor_qnor_cnor_csnorsdcardmux>sdcard_d0sdcard_d1sdcard_d2sdcard_d3sdcard_cmdsdcard_clksdcardsdiomux2sdio_d0sdio_d1sdio_d2sdio_d3sdio_cmdsdio_clksdiosdio_irqmux sdio_irqsdiouart_a  muxuart_tx_auart_rx_auart_auart_a_cts_rts  muxuart_cts_auart_rts_auart_auart_bmuxuart_tx_buart_rx_buart_buart_b_cts_rtsmuxuart_cts_buart_rts_buart_buart_cmuxuart_tx_cuart_rx_cuart_cuart_c_cts_rtsmuxuart_cts_cuart_rts_cuart_ci2c_amuxi2c_sck_ai2c_sda_ai2c_ai2c_bmuxi2c_sck_bi2c_sda_bi2c_bi2c_cmuxi2c_sck_ci2c_sda_ci2c_ceth_cmuxeth_mdioeth_mdceth_clk_rx_clketh_rx_dveth_rxd0eth_rxd1eth_rxd2eth_rxd3eth_rgmii_tx_clketh_tx_eneth_txd0eth_txd1eth_txd2eth_txd3ethpwm_amuxpwm_apwm_apwm_bmuxpwm_bpwm_bpwm_cmuxpwm_cpwm_cpwm_dmuxpwm_dpwm_dpwm_emuxpwm_epwm_epwm_f_clkmux pwm_f_clkpwm_fpwm_f_xmuxpwm_f_xpwm_fhdmi_hpdmux hdmi_hpd hdmi_hpdhdmi_i2cmuxhdmi_sdahdmi_scl hdmi_i2ci2s_am_clkmux i2s_am_clki2s_outi2s_out_ao_clkmuxi2s_out_ao_clki2s_outi2s_out_lr_clkmuxi2s_out_lr_clki2s_outi2s_out_ch01mux i2s_out_ch01i2s_outi2sout_ch23_zmuxi2sout_ch23_zi2s_outi2sout_ch45_zmuxi2sout_ch45_zi2s_outi2sout_ch67_zmuxi2sout_ch67_zi2s_outspdif_out_ao_hmux spdif_out_h spdif_outeth-phy-mux,mdio-mux-mmioregmdio-mux D\mdio@e40908ffD  ethernet-phy@84,ethernet-phy-id0181.4400ethernet-phy-ieee802.3-c22D*dmdio@2009087fD  hiubus@c883c000 ,simple-busDȃ  =ȃ mailbox@404,,amlogic,meson-gx-mhuamlogic,meson-gxbb-mhuDL$4clock-controller@0#,amlogic,gxl-clkcamlogic,gxbb-clkcDethernet@c9410000;,amlogic,meson-gx-dwmacamlogic,meson-gxbb-dwmacsnps,dwmac DAȃE@ @macirqEokay$stmmacethclkin0clkin1PrmiiYmdio ,snps,dwmac-mdioapb@d0000000 ,simple-busD  = mmc@70000,,amlogic,meson-gx-mmcamlogic,meson-gxbb-mmcD  Eokay^ coreclkin0clkin1LVdefault dnmmc@72000,,amlogic,meson-gx-mmcamlogic,meson-gxbb-mmcD  Eokay_ coreclkin0clkin1LVdefaultdn 0mmc@74000,,amlogic,meson-gx-mmcamlogic,meson-gxbb-mmcD@  Eokay` coreclkin0clkin1LVdefaultdn gpu@c0000%,amlogic,meson-gxbb-maliarm,mali-450D x1@gpgpmmupppmupp0ppmmu0pp1ppmmu1pp2ppmmu2 j buscore dfjf 4'vpu@d0100000+,amlogic,meson-gxl-vpuamlogic,meson-gx-vpu0Dȃȃ vpuhhidmc  port@0DendpointI &&port@1DendpointI!##hdmi-tx@c883a0003,amlogic,meson-gxl-dw-hdmiamlogic,meson-gx-dw-hdmiDȃ 9  EdisabledY""O"B`hdmitx_apbhdmitxhdmitx_phy? Misfriahbvenciport@0DendpointI#!!port@1Daliasesl/soc/aobus@c8100000/serial@4c0t/soc/cbus@c1100000/serial@84c0chosen|serial0:115200n8memory@0ymemoryDregulator-vddio_boot,regulator-fixed VDDIO_BOOTw@w@regulator-vddao_3v3,regulator-fixed VDDAO_3V32Z2Zregulator-vddio_ao18,regulator-fixed VDDIO_AO18w@w@regulator-vcc_3v3,regulator-fixedVCC_3V32Z2Zemmc-pwrseq,mmc-pwrseq-emmc #wifi32k ,pwm-clock$w6%%sdio-pwrseq,mmc-pwrseq-simple U% ext_clockcvbs-connector,composite-video-connectorportendpointI&   interrupt-parent#address-cells#size-cellscompatiblemodelrangesregno-mapreusablesizealignmentlinux,cma-defaultdevice_typeenable-methodnext-level-cacheclockslinux,phandleinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsmboxesshmemclock-indices#thermal-sensor-cells#reset-cellsstatuspinctrl-0pinctrl-namesuart-has-rtscts#pwm-cells#io-channel-cellsclock-namesvref-supplyinterrupt-controller#interrupt-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesgroupsfunctionmux-maskmdio-parent-busmax-speed#mbox-cellsinterrupt-namesphy-modephy-handlebus-widthcap-sd-highspeedmax-frequencynon-removabledisable-wpmmc-pwrseqvmmc-supplyvqmmc-supplycd-gpioscd-invertedcap-mmc-highspeedmmc-ddr-1_8vmmc-hs200-1_8vassigned-clocksassigned-clock-parentsassigned-clock-ratesremote-endpointresetsreset-namesserial0serial1stdout-pathregulator-nameregulator-min-microvoltregulator-max-microvoltreset-gpiospwms