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dma-rangesmodelcompatibleinterrupt-parent#address-cells#size-cells#clock-cellsclock-frequencyclock-output-nameslinux,phandleregstatusframe-numberinterruptsinterrupt-names#mbox-cellsclocksclock-names#iommu-cells#global-interruptsdma-coherentpower-domains#interrupt-cellsinterrupt-controllermsi-controllerslave-moderemote-endpointiommusreg-namescpudevice_typebus-rangelinux,pci-domaininterrupt-map-maskinterrupt-mapmsi-parentiommu-map-maskiommu-mapmboxesshmemclock-indicesnum-domains#power-domain-cells#thermal-sensor-cellspolling-delaypolling-delay-passivethermal-sensors#dma-cells#dma-channels#dma-requestsi2c-sda-hold-time-nsarm,hbiarm,vexpress,sitearm,v2m-memory-mapregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-ondebounce_intervalwakeup-sourcelinux,codelabelgpioslinux,part-probebank-widthphy-modereg-io-widthsmsc,irq-active-highsmsc,irq-push-pullvdd33a-supplyvddvario-supplyassigned-clocksassigned-clock-parentsoffsetlinux,default-triggerdefault-statemax-frequencyvmmc-supplygpio-controller#gpio-cellsserial0stdout-pathmethodentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-idle-statescapacity-dmips-mhzinterrupt-affinity