}8v4(u(hisilicon,hi6220-hikeyhisilicon,hi6220 +7HiKey Development Boardpsci arm,psci-0.2=smccpus+cpu-mapcluster0core0Dcore1Dcore2Dcore3Dcluster1core0Dcore1Dcore2Dcore3D idle-statesHpscicpu-sleeparm,idle-stateUf}  cluster-sleeparm,idle-stateUf} cpu@0arm,cortex-a53arm,armv8cpupsci   +=L \7cpu@1arm,cortex-a53arm,armv8cpupsci  L cpu@2arm,cortex-a53arm,armv8cpupsci  L cpu@3arm,cortex-a53arm,armv8cpupsci  L cpu@100arm,cortex-a53arm,armv8cpupsci L cpu@101arm,cortex-a53arm,armv8cpupsci L cpu@102arm,cortex-a53arm,armv8cpupsci L cpu@103arm,cortex-a53arm,armv8cpupsci L   l2-cache0cache  l2-cache1cachecpu_opp_tableoperating-points-v2v  opp00 eހ opp01ހ opp02+s@ opp0398p` opp04GKP interrupt-controller@f6801000 arm,gic-400@ @ `   timerarm,armv8-timer 0   soc simple-bus+sram@fff80000!hisilicon,hi6220-sramctrlsyscon ao_ctrl@f7800000hisilicon,hi6220-aoctrlsyscon sys_ctrl@f7030000 hisilicon,hi6220-sysctrlsyscon media_ctrl@f4410000"hisilicon,hi6220-mediactrlsysconAPPpm_ctrl@f7032000hisilicon,hi6220-pmctrlsyscon medianoc_ade@f4520000sysconR@OOstub_clockhisilicon,hi6220-stub-clkmbox-tx   uart@f8015000arm,pl011arm,primecellP $$$%uartclkapb_pclkuart@f7111000arm,pl011arm,primecell %%uartclkapb_pclk1default ?IokP)`рbluetooth ti,wl1835-st uuart@f7112000arm,pl011arm,primecell  &%uartclkapb_pclk1default?Iok LS-UART0uart@f7113000arm,pl011arm,primecell0 '%uartclkapb_pclk1default?Iok LS-UART1uart@f7114000arm,pl011arm,primecell@ (%uartclkapb_pclk1default? Idisabledtimer@f8008000arm,sp804arm,primecell%timer1timer2apb_pclkrtc@f8003000arm,pl031arm,primecell0  % %apb_pclkrtc@f8004000arm,pl031arm,primecell@ & %apb_pclkpinmux@f7010000pinctrl-single|+ pPX`hpx!+08Jz~1default? !"#**gpio-rangeboot_sel_pmx_funcemmc_pmx_funcP  $88sd_pmx_func0  ==sd_pmx_idle0  @@sdio_pmx_func0(,048<EEsdio_pmx_idle0(,048<HHisp_pmx_func$(,048<@DHLPTX\`hkadc_ssi_pmx_funch  codec_clk_pmx_funcl!!codec_pmx_func ptx|fm_pmx_func bt_pmx_func pwm_in_pmx_func""bl_pwm_pmx_func##uart0_pmx_funcuart1_pmx_func uart2_pmx_func uart3_pmx_func uart4_pmx_func uart5_pmx_funci2c0_pmx_func..i2c1_pmx_func00i2c2_pmx_func22spi0_pmx_func ++pinmux@f7010800pinconf-single+ 1default?$%&'(boot_sel_cfg_func3Pkp$$hkadc_ssi_cfg_funcl3Pkp%%emmc_clk_cfg_func3Pk p99emmc_cfg_funcH  $(3Pkp::emmc_rst_cfg_func,3Pkp;;sd_clk_cfg_func 3Pk0p>>sd_clk_cfg_idle 3PkpAAsd_cfg_func( 3Pk p??sd_cfg_idle( 3PkpBBsdio_clk_cfg_func43Pk pFFsdio_clk_cfg_idle43PkpIIsdio_cfg_func(8<@DH3PkpGGsdio_cfg_idle(8<@DH3PkpJJisp_cfg_func1x(,048<@DHLPX\`d3Pkpisp_cfg_idle1483Pkpisp_cfg_func2T3Pkpcodec_clk_cfg_funcp3Pkp&&codec_clk_cfg_idlep3Pkpcodec_cfg_func1t3Pkpcodec_cfg_func2x|3Pkpcodec_cfg_idle2x|3Pkpfm_cfg_func 3Pkpbt_cfg_func 3Pkpbt_cfg_idle 3Pkppwm_in_cfg_func3Pkp''bl_pwm_cfg_func3Pkp((uart0_cfg_func13Pkpuart0_cfg_func23Pkpuart1_cfg_func13Pkpuart1_cfg_func23Pkpuart2_cfg_func 3Pkpuart3_cfg_func 3Pkpuart4_cfg_func 3Pkpuart5_cfg_func3Pkpi2c0_cfg_func3Pkp//i2c1_cfg_func3Pkp11i2c2_cfg_func3Pkp33spi0_cfg_func 3Pkp,,pinmux@f8001800pinconf-singlex+ 1default?)rstout_n_cfg_func3Pkp))pmu_peri_en_cfg_func3Pkpsysclk0_en_cfg_func3Pkpjtag_tdo_cfg_func 3Pk prf_reset_cfg_funcpt3Pkpgpio@f8011000arm,pl061arm,primecell 4 %apb_pclkOPWR_HOLDDSI_SELUSB_HUB_RESET_NUSB_SELHDMI_PDWL_REG_ONPWRON_DET5V_HUB_EN44gpio@f8012000arm,pl061arm,primecell  5 %apb_pclk:SD_DETHDMI_INTPMU_IRQ_NWL_HOST_WAKENCNCNCBT_REG_ONgpio@f8013000arm,pl061arm,primecell0 6 %apb_pclkBGPIO-AGPIO-BGPIO-CGPIO-DGPIO-EUSB_ID_DETUSB_VBUS_DETGPIO-Hgpio@f8014000arm,pl061arm,primecell@ 7*P %apb_pclk%GPIO3_0NCNCNCWLAN_ACTIVENCNCWWgpio@f7020000arm,pl061arm,primecell 8*X %apb_pclk?USER_LED1USER_LED2USER_LED3USER_LED4SD_SELNCNCBT_ACTIVEVVgpio@f7021000arm,pl061arm,primecell 9*` %apb_pclk?NCNC[UART1_RxD][UART1_TxD][AUX_SSI1]NC[PCM_CLK][PCM_FS]gpio@f7022000arm,pl061arm,primecell  :*h %apb_pclk=[SPI0_DIN][SPI0_DOUT][SPI0_CS][SPI0_SCLK]NCNCNCGPIO-G--gpio@f7023000arm,pl061arm,primecell0 ;*p %apb_pclk$NCNCNCNC[PCM_DI][PCM_DO]NCNCgpio@f7024000arm,pl061arm,primecell@ < *x* %apb_pclkNC[CEC_CLK_19_2MHZ]NCgpio@f7025000arm,pl061arm,primecellP =* %apb_pclk'GPIO-JGPIO-LNCNCNCNC[ISP_CCLK0]gpio@f7026000arm,pl061arm,primecell` > ** %apb_pclk?BOOT_SEL[ISP_CCLK1]GPIO-IGPIO-KNCNC[I2C2_SDA][I2C2_SCL]gpio@f7027000arm,pl061arm,primecellp ? ** %apb_pclk"[I2C3_SDA][I2C3_SCL]NCNCNCgpio@f7028000arm,pl061arm,primecell @ *!*+ %apb_pclk8[BT_PCM_XFS][BT_PCM_DI][BT_PCM_DO]NCNCNCNCGPIO-Fgpio@f7029000arm,pl061arm,primecell A*0 %apb_pclkh[UART0_RX][UART0_TX][BT_UART1_CTS][BT_UART1_RTS][BT_UART1_RX][BT_UART1_TX][UART0_CTS][UART0_RTS]gpio@f702a000arm,pl061arm,primecell B*8 %apb_pclkZ[UART0_RxD][UART0_TxD][I2C0_SCL][I2C0_SDA][I2C1_SCL][I2C1_SDA][I2C2_SCL][I2C2_SDA]gpio@f702b000arm,pl061arm,primecell C0*J*z*~ %apb_pclk NCgpio@f702c000arm,pl061arm,primecell D* %apb_pclkgpio@f702d000arm,pl061arm,primecell E* %apb_pclkgpio@f702e000arm,pl061arm,primecell F* %apb_pclkgpio@f702f000arm,pl061arm,primecell G* %apb_pclkspi@f7106000arm,pl022arm,primecell` 2 %apb_pclk1default?+, -Ioki2c@f7100000snps,designware-i2c , ,1default?./Ioki2c@f7101000snps,designware-i2c -,1default?01Ioki2c@f7102000snps,designware-i2c  .,1default?23Iok+adv7533@39 adi,adv75339  4portendpoint5SSusbphyhisilicon,hi6220-usb-phy)6477usb@f72c0000hisilicon,hi6220-usb,P7 Uusb2-phy%otg_otggv Mmailbox@f7510000hisilicon,hi6220-mbox Q ^dwmmc0@f723d000hisilicon,hi6220-dw-mshc# H%ciubiureset1default?89:;<dwmmc1@f723e000hisilicon,hi6220-dw-mshc4# I+%ciubiureset 1defaultidle ?=>? @AB&3@CDM Xdwmmc2@f723f000hisilicon,hi6220-dw-mshc# J%ciubiureset 1defaultidle ?EFG HIJKaL+wlcore@2 ti,wl1835 tsensor@0,f7030700hisilicon,tsensor  %thermal_clklMMthermal-zonescls0d Mtripstrip-point@0passivetrip-point@1$passiveNNcooling-mapsmap0N ade@f4100000hisilicon,hi6220-adex ade_baseOP sPPP(%clk_ade_coreclk_codec_jpegclk_ade_pixPPP`u**IokportendpointQRRdsi@f4107800hisilicon,hi6220-dsixP%pclkIokports+port@0endpointRQQport@1endpoint@0S55aliases/soc/uart@f8015000'/soc/uart@f7111000//soc/uart@f71120007/soc/uart@f7113000chosen?serial3:115200n8memory@0memory` `A"reserved-memory+ramoops@0x21f00000ramoops!KWdlinux,cmashared-dma-poolpqyreboot-mode-syscon@5f01000sysconsimple-mfdreboot-modesyscon-reboot-modewfUwfUwfUregulator@0regulator-fixedSYS_5VLK@LK@ TTregulator@1regulator-fixedVDD_3V32Z2Z !TKKregulator@2regulator-fixed5V_HUBLK@LK@ 4 !T66wl1835-pwrseqmmc-pwrseq-simple ,4U %ext_clock8 LLleds gpio-ledsuser_led4 user_led4 |V Kheartbeatuser_led3 user_led3 |VKmmc0user_led2 user_led2 |VKmmc1user_led1 user_led1 |VKcpu0wlan_active_led wifi_active |WKphy0txaoffbt_active_led bt_active |VKhci0rxaoffpmic@f8000000hisilicon,hi655x-pmic oUUregulatorsLDO2 LDO2_2V8&%0zxLDO7 LDO7_SDIOw@2ZzxCCLDO10 LDO10_2V85w@-zhDDLDO13 LDO13_1V8j0zxLDO14 LDO14_2V8&%0zxLDO15 LDO15_1V8j0 zxLDO17 LDO17_2V5&%0zxLDO19 LDO19_3V0w@-zh<<LDO21 LDO21_1V8-P zxLDO22 LDO22_1V2 O zxfirmwareopteelinaro,optee-tz=smc compatibleinterrupt-parent#address-cells#size-cellsmodelmethodcpuentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uslinux,phandlewakeup-latency-usdevice_typeregenable-methodnext-level-cacheclocksoperating-points-v2cooling-min-levelcooling-max-level#cooling-cellscpu-idle-statesdynamic-power-coefficientopp-sharedopp-hzopp-microvoltclock-latency-ns#interrupt-cellsinterrupt-controllerinterruptsranges#clock-cells#reset-cellshisilicon,hi6220-clk-srammbox-namesmboxesclock-namespinctrl-namespinctrl-0statusassigned-clocksassigned-clock-ratesenable-gpioslabel#pinctrl-cells#gpio-range-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,gpio-range#pinctrl-single,gpio-range-cellspinctrl-single,pinspinctrl-single,bias-pulldownpinctrl-single,bias-pulluppinctrl-single,drive-strengthgpio-controller#gpio-cellsgpio-line-namesgpio-rangesbus-idenable-dmanum-cscs-gpiosi2c-sda-hold-time-nspd-gpioadi,dsi-lanesremote-endpoint#phy-cellsphy-supplyhisilicon,peripheral-sysconphysphy-namesdr_modeg-rx-fifo-sizeg-np-tx-fifo-sizeg-tx-fifo-size#mbox-cellsresetsreset-namescap-mmc-highspeednon-removablebus-widthvmmc-supplypinctrl-1card-detect-delaycap-sd-highspeedsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50vqmmc-supplydisable-wpcd-gpiosmmc-pwrseq#thermal-sensor-cellspolling-delaypolling-delay-passivesustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicereg-nameshisilicon,noc-syscondma-coherentserial0serial1serial2serial3stdout-pathrecord-sizeconsole-sizeftrace-sizereusablelinux,cma-defaultoffsetmode-normalmode-bootloadermode-recoveryregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onregulator-always-onvin-supplyreset-gpiospower-off-delay-uslinux,default-triggerdefault-statepmic-gpiosregulator-enable-ramp-delay