8T(:rockchip,rk3399-evbrockchip,rk3399google,rk3399evb-rev2 +!7Rockchip RK3399 Evaluation Boardaliases=/i2c@ff3c0000B/i2c@ff110000G/i2c@ff120000L/i2c@ff130000Q/i2c@ff3d0000V/i2c@ff140000[/i2c@ff150000`/i2c@ff160000e/i2c@ff3e0000j/serial@ff180000r/serial@ff190000z/serial@ff1a0000/serial@ff1b0000/serial@ff370000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1cpu@0cpuarm,cortex-a53arm,armv8pscicpu@1cpuarm,cortex-a53arm,armv8pscicpu@2cpuarm,cortex-a53arm,armv8pscicpu@3cpuarm,cortex-a53arm,armv8pscicpu@100cpuarm,cortex-a72arm,armv8psci cpu@101cpuarm,cortex-a72arm,armv8psci pmu_a53arm,cortex-a53-pmu pmu_a72arm,cortex-a72-pmu psci arm,psci-1.0smctimerarm,armv8-timer@   xin24m fixed-clockn6 xin24mamba simple-bus+*dma-controller@ff6d0000arm,pl330arm,primecellm@ 1   Pe?> disabled::qos@ffa74000syscon@ IIqos@ffa58000syscon GGqos@ffa5c000syscon HHqos@ffa90000syscon JJqos@ffa98000syscon @@qos@ffaa0000syscon KKqos@ffaa0080syscon LLqos@ffaa8000syscon MMqos@ffaa8080syscon NNqos@ffab0000syscon AAqos@ffab0080syscon BBqos@ffab8000syscon CCqos@ffac0000syscon DDqos@ffac0080syscon EEqos@ffac8000syscon OOqos@ffac8080syscon PPqos@ffad0000syscon QQqos@ffae0000syscon FFpower-management@ff310000&rockchip,rk3399-pmusysconsimple-mfd1power-controller!rockchip,rk3399-power-controller+pd_iep@34"@pd_rga@33!ABpd_vcodec@31Cpd_vdu@32 DEpd_gpu@35#Fpd_emmc@23Gpd_gmac@22fHpd_sd@27LIpd_vio@15+pd_hdcp@21rJpd_isp0@19KLpd_isp1@20MNpd_tcpc0@RK3399_PD_TCPC0~}pd_tcpc1@RK3399_PD_TCPC1 pd_vo@16+pd_vopb@17OPpd_vopl@18Qsyscon@ff320000)rockchip,rk3399-pmugrfsysconsimple-mfd2+__io-domains&rockchip,rk3399-pmu-io-voltage-domain disabledspi@ff350000(rockchip,rk3399-spirockchip,rk3066-spi5RRVR  R R >otp-outf??uart0uart0-xfer if""uart0-ctsfuart0-rtsfuart1uart1-xfer  i f##uart2auart2a-xfer i fuart2buart2b-xfer ifuart2cuart2c-xfer if$$uart3uart3-xfer if%%uart3-ctsfuart3-rtsfuart4uart4-xfer ifWWuarthdcpuarthdcp-xfer ifpwm0pwm0-pinf[[vop0-pwm-pinfpwm1pwm1-pinf\\vop1-pwm-pinfpwm2pwm2-pinf]]pwm3apwm3a-pinf^^pwm3bpwm3b-pinfpciepci-clkreqnfpci-clkreqnbfpmicpmic-int-lipmic-dvs2jusb2vcc5v0-host-enfoobacklightpwm-backlight  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~ k #laexternal-gmac-clock fixed-clocksY@  clkin_gmacvdd-centerpwm-regulator#ma (vdd_center7 5O\g{okayvcc3v3-sysregulator-fixed (vcc3v3_sysg{72ZO2Zvcc5v0-sysregulator-fixed (vcc5v0_sysg{7LK@OLK@ppvcc5v0-host-regulatorregulator-fixed ndefaulto (vcc5v0_hostp``vcc-phy-regulatorregulator-fixed(vcc_phyg{ compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4cpudevice_typeregenable-method#cooling-cellsclockslinux,phandleinterruptsarm,no-tick-in-suspendclock-frequencyclock-output-names#clock-cellsranges#dma-cellsclock-namesreg-names#interrupt-cellsaspm-no-l0sbus-rangeinterrupt-namesinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapphysphy-namesresetsreset-namesstatusep-gpiosnum-lanespinctrl-namespinctrl-0interrupt-controllerpower-domainsrockchip,grfassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delaymax-frequencyfifo-deptharasan,soc-ctl-sysconassigned-clock-ratesbus-widthmmc-hs400-1_8vmmc-hs400-enhanced-strobenon-removabledr_modephy_typesnps,dis_enblslpm_quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis-del-phy-power-chg-quirkmsi-controlleraffinity#io-channel-cellsreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cells#power-domain-cellspm_qos#pwm-cells#reset-cells#phy-cellsrockchip,typec-conn-dirrockchip,usb3tousb2-enrockchip,external-psmrockchip,pipe-statusdmasdma-namesrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsbrightness-levelsdefault-brightness-levelenable-gpiospwmsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onenable-active-highvin-supply