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#address-cells#size-cellsmodelcompatiblestdout-pathgpio0gpio1serial0serial1device_typereginterrupts-extendedcontrollerinterrupt-parentpcie-mem-aperturepcie-io-aperturerangesclocksstatuscache-unifiedcache-levelarm,double-linefill-incrarm,double-linefill-wraparm,double-linefillprefetch-datainterrupts#interrupt-cellsinterrupt-controllerlinux,phandlecell-indexpinctrl-namespinctrl-0spi-max-frequencym25p,fast-readtimeout-msclock-frequencygpio-controller#gpio-cellsreg-shiftreg-io-widthmarvell,pinsmarvell,functionngpios#clock-cellsmsi-controllerclock-namesphyphy-modevcc-supplydmacap,memcpydmacap,xordmacap,memsetreg-namestarget-supplyclock-output-namesmrvl,clk-delay-cyclescd-gpiosno-1-8-vwp-invertedbus-widthmsi-parentbus-rangeassigned-addressesinterrupt-map-maskinterrupt-mapmarvell,pcie-portmarvell,pcie-lanegpio-fan,speed-mapenable-methodregulator-nameregulator-min-microvoltregulator-max-microvoltenable-active-highregulator-always-ongpiovin-supply