5k81(w1Altera SOCFPGA Arria 10"!altr,socfpga-arria10altr,socfpgachosen ,earlyprintk5serial1:115200n8aliasesA/soc/serial0@ffc02000I/soc/serial1@ffc02100memoryQmemory]@cpusaaltr,socfpga-a10-smpcpu@0!arm,cortex-a9Qcpu]ocpu@1!arm,cortex-a9Qcpu]ointc@ffffd000!arm,cortex-a9-gic]soc !simple-busQsocamba !arm,amba-buspdma@ffda1000!arm,pl330arm,primecell]`STUVWXYZ clkmgr@ffd04000 !altr,clk-mgr]@clockscb_intosc_hs_div2_clk !fixed-clock  cb_intosc_ls_clk !fixed-clockf2s_free_clk !fixed-clockosc1 !fixed-clock }x@main_pll!altr,socfpga-a10-pll-clock ]@main_mpu_base_clk!altr,socfpga-a10-perip-clk "@   main_noc_base_clk!altr,socfpga-a10-perip-clk "D   main_emaca_clk!altr,socfpga-a10-perip-clk]hmain_emacb_clk!altr,socfpga-a10-perip-clk]lmain_emac_ptp_clk!altr,socfpga-a10-perip-clk]pmain_gpio_db_clk!altr,socfpga-a10-perip-clk]tmain_sdmmc_clk!altr,socfpga-a10-perip-clk]xmain_s2f_usr0_clk!altr,socfpga-a10-perip-clk]|main_s2f_usr1_clk!altr,socfpga-a10-perip-clk]main_hmc_pll_ref_clk!altr,socfpga-a10-perip-clk]main_periph_ref_clk!altr,socfpga-a10-perip-clk]periph_pll!altr,socfpga-a10-pll-clock]peri_mpu_base_clk!altr,socfpga-a10-perip-clk "@   peri_noc_base_clk!altr,socfpga-a10-perip-clk "D   peri_emaca_clk!altr,socfpga-a10-perip-clk]peri_emacb_clk!altr,socfpga-a10-perip-clk]peri_emac_ptp_clk!altr,socfpga-a10-perip-clk]peri_gpio_db_clk!altr,socfpga-a10-perip-clk]peri_sdmmc_clk!altr,socfpga-a10-perip-clk]peri_s2f_usr0_clk!altr,socfpga-a10-perip-clk]peri_s2f_usr1_clk!altr,socfpga-a10-perip-clk]peri_hmc_pll_ref_clk!altr,socfpga-a10-perip-clk]mpu_free_clk!altr,socfpga-a10-perip-clk  ]`noc_free_clk!altr,socfpga-a10-perip-clk  ]ds2f_user1_free_clk!altr,socfpga-a10-perip-clk ]sdmmc_free_clk!altr,socfpga-a10-perip-clk *]l4_sys_free_clk!altr,socfpga-a10-perip-clk*l4_main_clk!altr,socfpga-a10-gate-clk "8Hl4_mp_clk!altr,socfpga-a10-gate-clk "8Hl4_sp_clk!altr,socfpga-a10-gate-clk "8Hmpu_periph_clk!altr,socfpga-a10-gate-clk*8Hsdmmc_clk!altr,socfpga-a10-gate-clk8qspi_clk!altr,socfpga-a10-gate-clk8 nand_clk!altr,socfpga-a10-gate-clk8 spi_m_clk!altr,socfpga-a10-gate-clk8 usb_clk!altr,socfpga-a10-gate-clk8s2f_usr1_clk!altr,socfpga-a10-gate-clk8ethernet@ff8000000!altr,socfpga-stmmacsnps,dwmac-3.72asnps,dwmac AD]  \Tmacirqdp@ stmmaceth  stmmacethokayrgmii"/<IVcpD|ethernet@ff8020000!altr,socfpga-stmmacsnps,dwmac-3.72asnps,dwmac AH]  ]Tmacirqdp@ stmmaceth! stmmaceth disabledethernet@ff8040000!altr,socfpga-stmmacsnps,dwmac-3.72asnps,dwmac AL]@  ^Tmacirqdp@ stmmaceth disabledgpio@ffc02900!snps,dw-apb-gpio]) disabledgpio-controller@0!snps,dw-apb-gpio-port] pgpio@ffc02a00!snps,dw-apb-gpio]* disabledgpio-controller@0!snps,dw-apb-gpio-port] qgpio@ffc02b00!snps,dw-apb-gpio]+ disabledgpio-controller@0!snps,dw-apb-gpio-port] ri2c@ffc02200!snps,designware-i2c]" i disabledi2c@ffc02300!snps,designware-i2c]# j disabledi2c@ffc02400!snps,designware-i2c]$ k disabledi2c@ffc02500!snps,designware-i2c]% l disabledi2c@ffc02600!snps,designware-i2c]& m disabledsdr@ffc25000!syscon]ϱsdramedac!altr,sdram-edac-a10l2-cache@fffff000!arm,pl310-cache] dwmmc0@ff808000!altr,socfpga-dw-mshc] bbiuciuokay sram@ffe00000 !mmio-sram]rstmgr@ffd05000 !altr,rst-mgr]P# snoop-control-unit@ffffc000!arm,cortex-a9-scu]sysmgr@ffd06000!altr,sys-mgrsyscon]`6b0timer@ffffc600!arm,cortex-a9-twd-timer]  timer0@ffc02700!snps,dw-apb-timer s]'timertimer1@ffc02800!snps,dw-apb-timer t](timertimer2@ffd00000!snps,dw-apb-timer u]timertimer3@ffd00100!snps,dw-apb-timer v]timerserial0@ffc02000!snps,dw-apb-uart]  nFP disabledserial1@ffc02100!snps,dw-apb-uart]! oFPokayusbphy@0]!usb-nop-xceivokayusb@ffb00000 !snps,dwc2] _otgh musb2-phy disabledusb@ffb40000 !snps,dwc2] `h musb2-phy disabledwatchdog@ffd00200 !snps,dw-wdt] w disabledwatchdog@ffd00300 !snps,dw-wdt] x disabled #address-cells#size-cellsmodelcompatiblebootargsstdout-pathserial0serial1device_typeregenable-methodnext-level-cache#interrupt-cellsinterrupt-controllerlinux,phandleinterrupt-parentrangesinterrupts#dma-cells#dma-channels#dma-requests#clock-cellsclock-frequencyclocksdiv-regfixed-dividerclk-gatealtr,sysmgr-sysconinterrupt-namesmac-addresssnps,multicast-filter-binssnps,perfect-filter-entriestx-fifo-depthrx-fifo-depthclock-namesresetsreset-namesstatusphy-modephy-addrtxd0-skew-pstxd1-skew-pstxd2-skew-pstxd3-skew-psrxd0-skew-psrxd1-skew-psrxd2-skew-psrxd3-skew-pstxen-skew-pstxc-skew-psrxdv-skew-psrxc-skew-psmax-frame-sizegpio-controller#gpio-cellssnps,nr-gpiosaltr,sdr-sysconcache-unifiedcache-levelnum-slotsbroken-cdbus-width#reset-cellsaltr,modrst-offsetcpu1-start-addrreg-shiftreg-io-width#phy-cellsphysphy-names