BH=x(=0Terasic DE-0(Atlas)#!altr,socfpga-cyclone5altr,socfpgachosen ,earlyprintk5serial0:115200n8aliasesA/soc/ethernet@ff702000K/soc/ethernet@ff702000U/soc/serial0@ffc02000]/soc/serial1@ffc03000e/soc/timer0@ffc08000l/soc/timer1@ffc09000s/soc/timer2@ffd00000z/soc/timer3@ffd01000memorymemory@cpusaltr,socfpga-smpcpu@0!arm,cortex-a9cpucpu@1!arm,cortex-a9cpuintc@fffed000!arm,cortex-a9-gicsoc !simple-bussocamba !arm,amba-buspdma@ffe01000!arm,pl330arm,primecell`hijklmno . 5apb_pclk**can@ffc00000 !bosch,d_can0. Adisabledcan@ffc01000 !bosch,d_can0. Adisabledclkmgr@ffd04000 !altr,clk-mgr@clocksosc1H !fixed-clockU}x@osc2H !fixed-clockf2s_periph_ref_clkH !fixed-clock  f2s_sdram_ref_clkH !fixed-clock  main_pllH!altr,socfpga-pll-clock.@mpuclkH!altr,socfpga-perip-clk. e H  mainclkH!altr,socfpga-perip-clk. e Ldbg_base_clkH!altr,socfpga-perip-clk. e Pmain_qspi_clkH!altr,socfpga-perip-clk.Tmain_nand_sdmmc_clkH!altr,socfpga-perip-clk.Xcfg_h2f_usr0_clkH!altr,socfpga-perip-clk.\periph_pllH!altr,socfpga-pll-clock .   emac0_clkH!altr,socfpga-perip-clk. emac1_clkH!altr,socfpga-perip-clk. per_qsi_clkH!altr,socfpga-perip-clk. per_nand_mmc_clkH!altr,socfpga-perip-clk. per_base_clkH!altr,socfpga-perip-clk. h2f_usr1_clkH!altr,socfpga-perip-clk. sdram_pllH!altr,socfpga-pll-clock .   ddr_dqs_clkH!altr,socfpga-perip-clk. ddr_2x_dqs_clkH!altr,socfpga-perip-clk. ddr_dq_clkH!altr,socfpga-perip-clk. h2f_usr2_clkH!altr,socfpga-perip-clk. mpu_periph_clkH!altr,socfpga-perip-clk. m))mpu_l2_ram_clkH!altr,socfpga-perip-clk. ml4_main_clkH!altr,socfpga-gate-clk.{`l3_main_clkH!altr,socfpga-perip-clk.ml3_mp_clkH!altr,socfpga-gate-clk. ed{`l3_sp_clkH!altr,socfpga-gate-clk. edl4_mp_clkH!altr,socfpga-gate-clk. ed{`$$l4_sp_clkH!altr,socfpga-gate-clk. ed{`""dbg_at_clkH!altr,socfpga-gate-clk. eh{`dbg_clkH!altr,socfpga-gate-clk. eh{`dbg_trace_clkH!altr,socfpga-gate-clk. el{`dbg_timer_clkH!altr,socfpga-gate-clk.{`cfg_clkH!altr,socfpga-gate-clk.{`h2f_user0_clkH!altr,socfpga-gate-clk.{` emac_0_clkH!altr,socfpga-gate-clk.{emac_1_clkH!altr,socfpga-gate-clk.{usb_mp_clkH!altr,socfpga-gate-clk.{ e++spi_m_clkH!altr,socfpga-gate-clk.{ e((can0_clkH!altr,socfpga-gate-clk.{ ecan1_clkH!altr,socfpga-gate-clk.{ e gpio_db_clkH!altr,socfpga-gate-clk.{ eh2f_user1_clkH!altr,socfpga-gate-clk.{sdmmc_clkH!altr,socfpga-gate-clk . {sdmmc_clk_dividedH!altr,socfpga-gate-clk.{m&&nand_x_clkH!altr,socfpga-gate-clk . { nand_clkH!altr,socfpga-gate-clk . { mqspi_clkH!altr,socfpga-gate-clk . { ddr_dqs_clk_gateH!altr,socfpga-gate-clk.{ddr_2x_dqs_clk_gateH!altr,socfpga-gate-clk.{ddr_dq_clk_gateH!altr,socfpga-gate-clk.{h2f_user2_clkH!altr,socfpga-gate-clk.{ethernet@ff7000000!altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmac  `p  smacirq. 5stmmaceth!  stmmaceth Adisabledethernet@ff7020000!altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmac  `p  xmacirq. 5stmmaceth!! stmmacethAokay#rgmii,5BO\ivDi2c@ffc04000!snps,designware-i2c@." Aokayadxl345@0 !adi,adxl345S#i2c@ffc05000!snps,designware-i2cP."  Adisabledi2c@ffc06000!snps,designware-i2c`."  Adisabledi2c@ffc07000!snps,designware-i2cp."  Adisabledgpio@ff708000!snps,dw-apb-gpiop.$Aokaygpio-controller@0!snps,dw-apb-gpio-port gpio@ff709000!snps,dw-apb-gpiop.$Aokaygpio-controller@0!snps,dw-apb-gpio-port --gpio@ff70a000!snps,dw-apb-gpiop.$Aokaygpio-controller@0!snps,dw-apb-gpio-port ##sdr@ffc25000!sysconP%%sdramedac!altr,sdram-edac% 'l2-cache@fffef000!arm,pl310-cache &#1 = M^ldwmmc0@ff704000!altr,socfpga-dw-mshcp@  .$&5biuciu{''sram@ffff0000 !mmio-sramspi@fff00000!snps,dw-apb-ssi .( Adisabledsnoop-control-unit@fffec000!arm,cortex-a9-scuspi@fff01000!snps,dw-apb-ssi .( Adisabledtimer@fffec600!arm,cortex-a9-twd-timer  .)timer0@ffc08000!snps,dw-apb-timer ."5timertimer1@ffc09000!snps,dw-apb-timer ."5timertimer2@ffd00000!snps,dw-apb-timer .5timertimer3@ffd01000!snps,dw-apb-timer .5timerserial0@ffc02000!snps,dw-apb-uart  ."**txrxAokayserial1@ffc03000!snps,dw-apb-uart0 ."**txrxrstmgr@ffd05000 !altr,rst-mgrP!!usbphy@0"!usb-nop-xceivAokay,,usb@ffb00000 !snps,dwc2 }.+5otg-, 2usb2-phy Adisabledusb@ffb40000 !snps,dwc2 .+5otg-, 2usb2-phyAokaywatchdog@ffd02000 !snps,dw-wdt  .Aokaywatchdog@ffd03000 !snps,dw-wdt0 . Adisabledsysmgr@ffd08000!altr,sys-mgrsysconЀ@<Ѐ  3-3-v-regulator!regulator-fixedL3.3V[2Zs2Z''leds !gpio-ledshps0 hps_led0  - heartbeat #address-cells#size-cellsmodelcompatiblebootargsstdout-pathethernet0ethernet1serial0serial1timer0timer1timer2timer3device_typeregenable-methodnext-level-cache#interrupt-cellsinterrupt-controllerlinux,phandleinterrupt-parentrangesinterrupts#dma-cells#dma-channels#dma-requestsclocksclock-namesstatus#clock-cellsclock-frequencydiv-regfixed-dividerclk-gateclk-phasealtr,sysmgr-sysconinterrupt-namesmac-addressresetsreset-namessnps,multicast-filter-binssnps,perfect-filter-entriestx-fifo-depthrx-fifo-depthphy-modephy-addrtxd0-skew-pstxd1-skew-pstxd2-skew-pstxd3-skew-psrxd0-skew-psrxd1-skew-psrxd2-skew-psrxd3-skew-pstxen-skew-pstxc-skew-psrxdv-skew-psrxc-skew-psmax-frame-sizespeed-modegpio-controller#gpio-cellssnps,nr-gpiosaltr,sdr-sysconcache-unifiedcache-levelarm,tag-latencyarm,data-latencyprefetch-dataprefetch-instrnum-slotsbroken-cdbus-widthcap-mmc-highspeedcap-sd-highspeedvmmc-supplyvqmmc-supplynum-csreg-shiftreg-io-widthdmasdma-names#reset-cellsaltr,modrst-offset#phy-cellsphysphy-namescpu1-start-addrregulator-nameregulator-min-microvoltregulator-max-microvoltlabellinux,default-trigger