:8/( }.Ncompulab,sbc-am57xcompulab,cl-som-am57xti,am5728ti,dra742ti,dra74ti,dra7&&7CompuLab CL-SOM-AM57x on SB-SOM-AM57xchosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/i2c@4807a000Q/ocp/i2c@4807c000V/ocp/serial@4806a000^/ocp/serial@4806c000f/ocp/serial@48020000n/ocp/serial@4806e000v/ocp/serial@48066000~/ocp/serial@48068000/ocp/serial@48420000/ocp/serial@48422000/ocp/serial@48424000/ocp/serial@4ae2b000&/ocp/ethernet@48484000/slave@48480200&/ocp/ethernet@48484000/slave@48480300/ocp/can@481cc000/ocp/can@481d0000/ocp/qspi@4b300000 /display#/ocp/dss@58000000/encoder@58060000memorymemory timerarm,armv7-timer0   &interrupt-controller@48211000arm,cortex-a15-gic H!H! H!@ H!`   & &interrupt-controller@48281000&ti,omap5-wugen-mputi,omap4-wugen-mpuH(& &socti,omap-inframpu ti,omap5-mpu.mpuocpti,dra7-l3-nocsimple-bus8.l3_main_1l3_main_2DE ? l4@4a000000ti,dra7-l4-cfgsimple-bus 8J"scm@2000ti,dra7-scm-coresimple-bus  8 scm_conf@0sysconsimple-bus 8 &pbias_regulatorti,pbias-dra7ti,pbias-omapSpbias_mmc_omap5Zpbias_mmc_omap5iw@- &clocksdss_deshdcp_clkti,gate-clockXpinmux@1400ti,dra7-padconfpinctrl-singleh ? &leds_pins_default| &i2c1_pins_default &i2c3_pins_default   &i2c4_pins_default   &tps659038_pins_default &mmc2_pins_defaultP &pinmux_qspi1_pins0t &cpsw_pins_defaultPTX\`dhlptx| &cpsw_pins_sleepPTX\`dhlptx| &davinci_mdio_pins_default &davinci_mdio_pins_sleep &pinmux_ads7846_pinsd &mcasp3_pins_default $(,0 &mcasp3_pins_sleep $(,0 &uart3_pins_defaultH L  &mmc1_pins_default@TX\`dhl| &pinmux_usb1_pins  &i2c5_pins_default   &lcd_pins_defaultd &pinmux_hdmi_pins  &pinmux_hdmi_conn_pins &scm_conf@1c04syscon cm_core_aon@5000ti,dra7-cm-core-aonP clocksatl_clkin0_ckti,dra7-atl-clock 7&7atl_clkin1_ckti,dra7-atl-clock 6&6atl_clkin2_ckti,dra7-atl-clock 5&5atl_clkin3_ckti,dra7-atl-clock 4&4hdmi_clkin_ck fixed-clock  %&%mlb_clkin_ck fixed-clock  &mlbp_clkin_ck fixed-clock  &pciesref_acs_clk_ck fixed-clock  N&Nref_clkin0_ck fixed-clock  9&9ref_clkin1_ck fixed-clock  :&:ref_clkin2_ck fixed-clock  ;&;ref_clkin3_ck fixed-clock  <&<rmii_clk_ck fixed-clock sdvenc_clkin_ck fixed-clock secure_32k_clk_src_ck fixed-clock  &sys_32k_ck fixed-clock  D&Dvirt_12000000_ck fixed-clock  r&rvirt_13000000_ck fixed-clock ]@virt_16800000_ck fixed-clock Y t&tvirt_19200000_ck fixed-clock $ u&uvirt_20000000_ck fixed-clock 1- s&svirt_26000000_ck fixed-clock  v&vvirt_27000000_ck fixed-clock  w&wvirt_38400000_ck fixed-clock I x&xsys_clkin2 fixed-clock X 8&8usb_otg_clkin_ck fixed-clock  ~&~video1_clkin_ck fixed-clock  .&.video1_m2_clkin_ck fixed-clock  $&$video2_clkin_ck fixed-clock  /&/video2_m2_clkin_ck fixed-clock  #&#dpll_abe_ckti,omap4-dpll-m4xen-clock & dpll_abe_x2_ckti,omap4-dpll-x2-clock  & dpll_abe_m2x2_ckti,divider-clock $6M & abe_clkti,divider-clock d z&zdpll_abe_m2_ckti,divider-clock $6M c&cdpll_abe_m3x2_ckti,divider-clock $6M & dpll_core_byp_mux ti,mux-clock , &dpll_core_ckti,omap4-dpll-core-clock  $,( &dpll_core_x2_ckti,omap4-dpll-x2-clock &dpll_core_h12x2_ckti,divider-clock?$<6M &mpu_dpll_hs_clk_divfixed-factor-clockz &dpll_mpu_ckti,omap5-mpu-dpll-clock `dlh &dpll_mpu_m2_ckti,divider-clock$p6M &mpu_dclk_divfixed-factor-clockz &dsp_dpll_hs_clk_divfixed-factor-clockz &dpll_dsp_byp_mux ti,mux-clock @ &dpll_dsp_ckti,omap4-dpll-clock 48@< &dpll_dsp_m2_ckti,divider-clock$D6M |&|iva_dpll_hs_clk_divfixed-factor-clockz &dpll_iva_byp_mux ti,mux-clock  &dpll_iva_ckti,omap4-dpll-clock  &dpll_iva_m2_ckti,divider-clock$6M &iva_dclkfixed-factor-clockz &dpll_gpu_byp_mux ti,mux-clock  &dpll_gpu_ckti,omap4-dpll-clock  &dpll_gpu_m2_ckti,divider-clock$6M h&hdpll_core_m2_ckti,divider-clock$06M &core_dpll_out_dclk_divfixed-factor-clockz &dpll_ddr_byp_mux ti,mux-clock  &dpll_ddr_ckti,omap4-dpll-clock  & dpll_ddr_m2_ckti,divider-clock $ 6M }&}dpll_gmac_byp_mux ti,mux-clock  !&!dpll_gmac_ckti,omap4-dpll-clock ! "&"dpll_gmac_m2_ckti,divider-clock"$6M e&evideo2_dclk_divfixed-factor-clock#z &video1_dclk_divfixed-factor-clock$z &hdmi_dclk_divfixed-factor-clock%z &per_dpll_hs_clk_divfixed-factor-clock z R&Rusb_dpll_hs_clk_divfixed-factor-clock z V&Veve_dpll_hs_clk_divfixed-factor-clockz &&&dpll_eve_byp_mux ti,mux-clock & '&'dpll_eve_ckti,omap4-dpll-clock ' (&(dpll_eve_m2_ckti,divider-clock($6M )&)eve_dclk_divfixed-factor-clock)z &dpll_core_h13x2_ckti,divider-clock?$@6Mdpll_core_h14x2_ckti,divider-clock?$D6M f&fdpll_core_h22x2_ckti,divider-clock?$T6M 0&0dpll_core_h23x2_ckti,divider-clock?$X6M q&qdpll_core_h24x2_ckti,divider-clock?$\6Mdpll_ddr_x2_ckti,omap4-dpll-x2-clock  *&*dpll_ddr_h11x2_ckti,divider-clock*?$(6Mdpll_dsp_x2_ckti,omap4-dpll-x2-clock +&+dpll_dsp_m3x2_ckti,divider-clock+$H6M &dpll_gmac_x2_ckti,omap4-dpll-x2-clock" ,&,dpll_gmac_h11x2_ckti,divider-clock,?$6M -&-dpll_gmac_h12x2_ckti,divider-clock,?$6Mdpll_gmac_h13x2_ckti,divider-clock,?$6Mdpll_gmac_m3x2_ckti,divider-clock,$6Mgmii_m_clk_divfixed-factor-clock-zhdmi_clk2_divfixed-factor-clock%z B&Bhdmi_div_clkfixed-factor-clock%z H&Hl3_iclk_divti,divider-clockd &l4_root_clk_divfixed-factor-clockzvideo1_clk2_divfixed-factor-clock.z @&@video1_div_clkfixed-factor-clock.z F&Fvideo2_clk2_divfixed-factor-clock/z A&Avideo2_div_clkfixed-factor-clock/z G&Gipu1_gfclk_mux ti,mux-clock 0 mcasp1_ahclkr_mux ti,mux-clock8123456789:;<=>Pmcasp1_ahclkx_mux ti,mux-clock8123456789:;<=>Pmcasp1_aux_gfclk_mux ti,mux-clock?@ABPtimer5_gfclk_mux ti,mux-clock0CD89:;<EFGHIXtimer6_gfclk_mux ti,mux-clock0CD89:;<EFGHI`timer7_gfclk_mux ti,mux-clock0CD89:;<EFGHIhtimer8_gfclk_mux ti,mux-clock0CD89:;<EFGHIpuart6_gfclk_mux ti,mux-clockJKdummy_ck fixed-clock clockdomainscm_core@8000ti,dra7-cm-core0clocksdpll_pcie_ref_ckti,omap4-dpll-clock   L&Ldpll_pcie_ref_m2ldo_ckti,divider-clockL$6M M&Mapll_pcie_in_clk_mux@4ae06118 ti,mux-clockMN O&Oapll_pcie_ckti,dra7-apll-clockOL  P&Poptfclk_pciephy1_32khz@4a0093b0ti,gate-clockD &optfclk_pciephy2_32khz@4a0093b8ti,gate-clockD &optfclk_pciephy_div@4a00821cti,divider-clockP Q&Qoptfclk_pciephy1_clk@4a0093b0ti,gate-clockP  &optfclk_pciephy2_clk@4a0093b8ti,gate-clockP  &optfclk_pciephy1_div_clk@4a0093b0ti,gate-clockQ  &optfclk_pciephy2_div_clk@4a0093b8ti,gate-clockQ  &apll_pcie_clkvcoldofixed-factor-clockPzapll_pcie_clkvcoldo_divfixed-factor-clockPzapll_pcie_m2_ckfixed-factor-clockPz &dpll_per_byp_mux ti,mux-clock RL S&Sdpll_per_ckti,omap4-dpll-clock S@DLH T&Tdpll_per_m2_ckti,divider-clockT$P6M U&Ufunc_96m_aon_dclk_divfixed-factor-clockUz &dpll_usb_byp_mux ti,mux-clock V W&Wdpll_usb_ckti,omap4-dpll-j-type-clock W X&Xdpll_usb_m2_ckti,divider-clockX$6M [&[dpll_pcie_ref_m2_ckti,divider-clockL$6M &dpll_per_x2_ckti,omap4-dpll-x2-clockT Y&Ydpll_per_h11x2_ckti,divider-clockY?$X6M Z&Zdpll_per_h12x2_ckti,divider-clockY?$\6M ^&^dpll_per_h13x2_ckti,divider-clockY?$`6M o&odpll_per_h14x2_ckti,divider-clockY?$d6M g&gdpll_per_m2x2_ckti,divider-clockY$P6M K&Kdpll_usb_clkdcoldofixed-factor-clockXz ]&]func_128m_clkfixed-factor-clockZz j&jfunc_12m_fclkfixed-factor-clockKzfunc_24m_clkfixed-factor-clockUz 3&3func_48m_fclkfixed-factor-clockKz J&Jfunc_96m_fclkfixed-factor-clockKzl3init_60m_fclkti,divider-clock[clkout2_clkti,gate-clock\l3init_960m_gfclkti,gate-clock] b&bdss_32khz_clkti,gate-clockD  dss_48mhz_clkti,gate-clockJ   &dss_dss_clkti,gate-clock^  &dss_hdmi_clkti,gate-clock_   &dss_video1_clkti,gate-clock`   &dss_video2_clkti,gate-clocka   &gpio2_dbclkti,gate-clockD`gpio3_dbclkti,gate-clockDhgpio4_dbclkti,gate-clockDpgpio5_dbclkti,gate-clockDxgpio6_dbclkti,gate-clockDgpio7_dbclkti,gate-clockDgpio8_dbclkti,gate-clockDmmc1_clk32kti,gate-clockD(mmc2_clk32kti,gate-clockD0mmc3_clk32kti,gate-clockD mmc4_clk32kti,gate-clockD(sata_ref_clkti,gate-clock  &usb_otg_ss1_refclk960mti,gate-clockb &usb_otg_ss2_refclk960mti,gate-clockb@ &usb_phy1_always_on_clk32kti,gate-clockD@ &usb_phy2_always_on_clk32kti,gate-clockD &usb_phy3_always_on_clk32kti,gate-clockD &atl_dpll_clk_mux ti,mux-clockD./%  d&datl_gfclk_mux ti,mux-clock cd  &gmac_gmii_ref_clk_divti,divider-clocke &gmac_rft_clk_mux ti,mux-clock./c%gpu_core_gclk_mux ti,mux-clock fgh gpu_hyd_gclk_mux ti,mux-clock fgh l3instr_ts_gclk_divti,divider-clockiP  mcasp2_ahclkr_mux ti,mux-clock8123456789:;<=>`mcasp2_ahclkx_mux ti,mux-clock8123456789:;<=>`mcasp2_aux_gfclk_mux ti,mux-clock?@AB`mcasp3_ahclkx_mux ti,mux-clock8123456789:;<=>h &mcasp3_aux_gfclk_mux ti,mux-clock?@ABh &mcasp4_ahclkx_mux ti,mux-clock8123456789:;<=>mcasp4_aux_gfclk_mux ti,mux-clock?@ABmcasp5_ahclkx_mux ti,mux-clock8123456789:;<=>xmcasp5_aux_gfclk_mux ti,mux-clock?@ABxmcasp6_ahclkx_mux ti,mux-clock8123456789:;<=>mcasp6_aux_gfclk_mux ti,mux-clock?@ABmcasp7_ahclkx_mux ti,mux-clock8123456789:;<=>mcasp7_aux_gfclk_mux ti,mux-clock?@ABmcasp8_ahclk_mux ti,mux-clock8123456789:;<=>mcasp8_aux_gfclk_mux ti,mux-clock?@ABmmc1_fclk_mux ti,mux-clockjK( k&kmmc1_fclk_divti,divider-clockk(dmmc2_fclk_mux ti,mux-clockjK0 l&lmmc2_fclk_divti,divider-clockl0dmmc3_gfclk_mux ti,mux-clockJK  m&mmmc3_gfclk_divti,divider-clockm dmmc4_gfclk_mux ti,mux-clockJK( n&nmmc4_gfclk_divti,divider-clockn(dqspi_gfclk_mux ti,mux-clockjo8 p&pqspi_gfclk_divti,divider-clockp8d &timer10_gfclk_mux ti,mux-clock,CD89:;<EFGH(timer11_gfclk_mux ti,mux-clock,CD89:;<EFGH0timer13_gfclk_mux ti,mux-clock,CD89:;<EFGHtimer14_gfclk_mux ti,mux-clock,CD89:;<EFGHtimer15_gfclk_mux ti,mux-clock,CD89:;<EFGHtimer16_gfclk_mux ti,mux-clock,CD89:;<EFGH0timer2_gfclk_mux ti,mux-clock,CD89:;<EFGH8timer3_gfclk_mux ti,mux-clock,CD89:;<EFGH@timer4_gfclk_mux ti,mux-clock,CD89:;<EFGHHtimer9_gfclk_mux ti,mux-clock,CD89:;<EFGHPuart1_gfclk_mux ti,mux-clockJK@uart2_gfclk_mux ti,mux-clockJKHuart3_gfclk_mux ti,mux-clockJKPuart4_gfclk_mux ti,mux-clockJKXuart5_gfclk_mux ti,mux-clockJKpuart7_gfclk_mux ti,mux-clockJKuart8_gfclk_mux ti,mux-clockJKuart9_gfclk_mux ti,mux-clockJKvip1_gclk_mux ti,mux-clockq vip2_gclk_mux ti,mux-clockq(vip3_gclk_mux ti,mux-clockq0clockdomainscoreaon_clkdmti,clockdomainXl4@4ae00000ti,dra7-l4-wkupsimple-bus 8Jcounter@4000ti,omap-counter32k@@ .counter_32kprm@6000 ti,dra7-prm`0 clockssys_clkin1 ti,mux-clockrstuvwx6 & abe_dpll_sys_clk_mux ti,mux-clock 8 y&yabe_dpll_bypass_clk_mux ti,mux-clockyD &abe_dpll_clk_mux ti,mux-clockyD  &abe_24m_fclkti,divider-clock  1&1aess_fclkti,divider-clockzx {&{abe_giclk_divti,divider-clock{t E&Eabe_lp_clk_divti,divider-clock   &abe_sys_clk_divti,divider-clock   2&2adc_gfclk_mux ti,mux-clock  8Dsys_clk1_dclk_divti,divider-clock @d &sys_clk2_dclk_divti,divider-clock8@d &per_abe_x1_dclk_divti,divider-clockc@d &dsp_gclk_divti,divider-clock|@d &gpu_dclkti,divider-clockh@d &emif_phy_dclk_divti,divider-clock}@d &gmac_250m_dclk_divti,divider-clocke@d &l3init_480m_dclk_divti,divider-clock[@d &usb_otg_dclk_divti,divider-clock~@d &sata_dclk_divti,divider-clock @d &pcie2_dclk_divti,divider-clock@d &pcie_dclk_divti,divider-clock@d &emu_dclk_divti,divider-clock @d &secure_32k_dclk_divti,divider-clock@d &clkoutmux0_clk_mux ti,mux-clockXX I&Iclkoutmux1_clk_mux ti,mux-clockX\clkoutmux2_clk_mux ti,mux-clockX` \&\custefuse_sys_gfclk_divfixed-factor-clock zeve_clk ti,mux-clock)hdmi_dpll_clk_mux ti,mux-clock 8d _&_mlb_clkti,divider-clock@4d =&=mlbp_clkti,divider-clock@0d >&>per_abe_x1_gfclk2_divti,divider-clockc@8d ?&?timer_sys_clk_divti,divider-clock D C&Cvideo1_dpll_clk_mux ti,mux-clock 8h `&`video2_dpll_clk_mux ti,mux-clock 8l a&awkupaon_iclk_mux ti,mux-clock  i&igpio1_dbclkti,gate-clockD8dcan1_sys_clk_mux ti,mux-clock 8 &timer1_gfclk_mux ti,mux-clock,CD89:;<EFGH@uart10_gfclk_mux ti,mux-clockJKclockdomainsaxi@0 simple-bus8QQ0 pcie@51000000 ti,dra7-pcieQ Q L rc_dbicsti_confconfigpci080 00.pcie1 pcie-phy0`interrupt-controller &axi@1 simple-bus8QQ00 disabledpcie@51000000 ti,dra7-pcieQ Q L rc_dbicsti_confconfigcdpci080000.pcie2 pcie-phy0`interrupt-controller &bandgap@4a0021e00J! J#, J#,J#txrxokaydefault  mmc@480b4000ti,omap4-hsmmcH @ Q.mmc2/0txrxokaydefaultmmc@480ad000ti,omap4-hsmmcH  Y.mmc3MNtxrx disabledmmc@480d1000ti,omap4-hsmmcH  [.mmc49:txrx disabledmmu@40d01000ti,dra7-dsp-iommu@  .mmu0_dsp1 disabledmmu@40d02000ti,dra7-dsp-iommu@   .mmu1_dsp1 disabledmmu@58882000ti,dra7-iommuX   .mmu_ipu12 disabledmmu@55082000ti,dra7-iommuU   .mmu_ipu22 disabledregulator-abb-mpu ti,abb-v3Zabb_mpu H2Y(J}J}J`J; JXDsetup-addresscontrol-addressint-addressefuse-addressldo-addressiH,@vregulator-abb-ivahd ti,abb-v3 Zabb_ivahd H2Y(J~4J~$J`J% J$pDsetup-addresscontrol-addressint-addressefuse-addressldo-addressi@H0regulator-abb-dspeve ti,abb-v3 Zabb_dspeve H2Y(J~0J~ J`J% J$lDsetup-addresscontrol-addressint-addressefuse-addressldo-addressi H0regulator-abb-gpu ti,abb-v3Zabb_gpu H2Y(J}J}J`J; JTDsetup-addresscontrol-addressint-addressefuse-addressldo-addressiHvspi@48098000ti,omap4-mcspiH  <.mcspi1@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3 disabledspi@4809a000ti,omap4-mcspiH  =.mcspi2 +,-.tx0rx0tx1rx1 disabledspi@480b8000ti,omap4-mcspiH  V.mcspi3tx0rx0 disabledspi@480ba000ti,omap4-mcspiH  +.mcspi4FGtx0rx0 disabledqspi@4b300000ti,dra7xxx-qspiK0\qspi_baseqspi_mmapX.qspifck Wokaydefaultlspi_flash@0spansion,m25p80jedec,spi-norlpartition@0uboot partition@c0000uboot environment partition@100000 reservedads7846@0default ti,ads7846`&   )2;K[k {Kcontrol-phy@4a002374ti,control-phy-pipe3J#tpower sysclk &ocp2scp@4a090000ti,omap-ocp2scp8J  .ocp2scp3phy@4A096000ti,phy-pipe3-sataJ `J ddJ h@phy_rxphy_txpll_ctrl sysclkrefclk &pciephy@4a094000ti,phy-pipe3-pcieJ @J Ddphy_rxphy_txLMQ4dpll_refdpll_ref_m2wkupclkrefclkdiv-clkphy-div &pciephy@4a095000ti,phy-pipe3-pcieJ PJ Tdphy_rxphy_txLMQ4dpll_refdpll_ref_m2wkupclkrefclkdiv-clkphy-div disabled &sata@4a141100snps,dwc-ahciJJ 1 sata-phy.sataokaycontrol-phy@0x4a003c40ti,control-phy-pcieJ<@J<J<4powercontrol_smapcie_pcs sysclk &control-pcie@0x4a003c44ti,control-phy-pcieJ