98,( ,(ti,dra72-evmti,dra722ti,dra72ti,dra7& 7TI DRA722chosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/i2c@4807a000Q/ocp/i2c@4807c000V/ocp/serial@4806a000^/ocp/serial@4806c000f/ocp/serial@48020000n/ocp/serial@4806e000v/ocp/serial@48066000~/ocp/serial@48068000/ocp/serial@48420000/ocp/serial@48422000/ocp/serial@48424000/ocp/serial@4ae2b000&/ocp/ethernet@48484000/slave@48480200&/ocp/ethernet@48484000/slave@48480300/ocp/can@481cc000/ocp/can@481d0000/ocp/qspi@4b300000 /connectormemorymemory@timerarm,armv7-timer0   &interrupt-controller@48211000arm,cortex-a15-gic H!H! H!@ H!`   &interrupt-controller@48281000&ti,omap5-wugen-mputi,omap4-wugen-mpuH(&socti,omap-inframpu ti,omap5-mpu%mpuocpti,dra7-l3-nocsimple-bus/%l3_main_1l3_main_2DE 6 l4@4a000000ti,dra7-l4-cfgsimple-bus /J"scm@2000ti,dra7-scm-coresimple-bus  / scm_conf@0sysconsimple-bus /pbias_regulatorti,pbias-dra7ti,pbias-omapJpbias_mmc_omap5Qpbias_mmc_omap5`w@x-clocksdss_deshdcp_clkti,gate-clockXpinmux@1400ti,dra7-padconfpinctrl-singleh ?pinmux_i2c1_pinspinmux_i2c5_pins  nand_default  $(,048<pinmux_usb1_pins pinmux_usb2_pins tps65917_pins_default$mmc1_pins_default8lTX\`dhmmc2_pins_defaultPdcan1_pins_defaultdcan1_pins_sleeppinmux_qspi1_pins8tx|pinmux_hdmi_pins pinmux_tpd12s015_pinspinmux_atl_pinspinmux_mcasp3_pins $(,0pinmux_mcasp3_sleep_pins $(,0cpsw_default`cpsw_sleep`davinci_mdio_default<@davinci_mdio_sleep<@scm_conf@1c04syscon cm_core_aon@5000ti,dra7-cm-core-aonP clocksatl_clkin0_ckti,dra7-atl-clock77atl_clkin1_ckti,dra7-atl-clock66atl_clkin2_ckti,dra7-atl-clock55atl_clkin3_ckti,dra7-atl-clock44hdmi_clkin_ck fixed-clock%%mlb_clkin_ck fixed-clockmlbp_clkin_ck fixed-clockpciesref_acs_clk_ck fixed-clockNNref_clkin0_ck fixed-clock99ref_clkin1_ck fixed-clock::ref_clkin2_ck fixed-clock;;ref_clkin3_ck fixed-clock<<rmii_clk_ck fixed-clocksdvenc_clkin_ck fixed-clocksecure_32k_clk_src_ck fixed-clocksys_32k_ck fixed-clockDDvirt_12000000_ck fixed-clockrrvirt_13000000_ck fixed-clock]@virt_16800000_ck fixed-clockYttvirt_19200000_ck fixed-clock$uuvirt_20000000_ck fixed-clock1-ssvirt_26000000_ck fixed-clockvvvirt_27000000_ck fixed-clockwwvirt_38400000_ck fixed-clockIxxsys_clkin2 fixed-clockX88usb_otg_clkin_ck fixed-clock~~video1_clkin_ck fixed-clock..video1_m2_clkin_ck fixed-clock$$video2_clkin_ck fixed-clock//video2_m2_clkin_ck fixed-clock##dpll_abe_ckti,omap4-dpll-m4xen-clock  dpll_abe_x2_ckti,omap4-dpll-x2-clock   dpll_abe_m2x2_ckti,divider-clock -D  abe_clkti,divider-clock [zzdpll_abe_m2_ckti,divider-clock -Dccdpll_abe_m3x2_ckti,divider-clock -D  dpll_core_byp_mux ti,mux-clock ,dpll_core_ckti,omap4-dpll-core-clock  $,(dpll_core_x2_ckti,omap4-dpll-x2-clockdpll_core_h12x2_ckti,divider-clock?<-Dmpu_dpll_hs_clk_divfixed-factor-clockq|dpll_mpu_ckti,omap5-mpu-dpll-clock `dlhdpll_mpu_m2_ckti,divider-clockp-Dmpu_dclk_divfixed-factor-clockq|dsp_dpll_hs_clk_divfixed-factor-clockq|dpll_dsp_byp_mux ti,mux-clock @dpll_dsp_ckti,omap4-dpll-clock 48@<dpll_dsp_m2_ckti,divider-clockD-D||iva_dpll_hs_clk_divfixed-factor-clockq|dpll_iva_byp_mux ti,mux-clock dpll_iva_ckti,omap4-dpll-clock dpll_iva_m2_ckti,divider-clock-Diva_dclkfixed-factor-clockq|dpll_gpu_byp_mux ti,mux-clock dpll_gpu_ckti,omap4-dpll-clock dpll_gpu_m2_ckti,divider-clock-Dhhdpll_core_m2_ckti,divider-clock0-Dcore_dpll_out_dclk_divfixed-factor-clockq|dpll_ddr_byp_mux ti,mux-clock dpll_ddr_ckti,omap4-dpll-clock   dpll_ddr_m2_ckti,divider-clock  -D}}dpll_gmac_byp_mux ti,mux-clock !!dpll_gmac_ckti,omap4-dpll-clock !""dpll_gmac_m2_ckti,divider-clock"-Deevideo2_dclk_divfixed-factor-clock#q|video1_dclk_divfixed-factor-clock$q|hdmi_dclk_divfixed-factor-clock%q|per_dpll_hs_clk_divfixed-factor-clock q|RRusb_dpll_hs_clk_divfixed-factor-clock q|VVeve_dpll_hs_clk_divfixed-factor-clockq|&&dpll_eve_byp_mux ti,mux-clock &''dpll_eve_ckti,omap4-dpll-clock '((dpll_eve_m2_ckti,divider-clock(-D))eve_dclk_divfixed-factor-clock)q|dpll_core_h13x2_ckti,divider-clock?@-Ddpll_core_h14x2_ckti,divider-clock?D-Dffdpll_core_h22x2_ckti,divider-clock?T-D00dpll_core_h23x2_ckti,divider-clock?X-Dqqdpll_core_h24x2_ckti,divider-clock?\-Ddpll_ddr_x2_ckti,omap4-dpll-x2-clock **dpll_ddr_h11x2_ckti,divider-clock*?(-Ddpll_dsp_x2_ckti,omap4-dpll-x2-clock++dpll_dsp_m3x2_ckti,divider-clock+H-Ddpll_gmac_x2_ckti,omap4-dpll-x2-clock",,dpll_gmac_h11x2_ckti,divider-clock,?-D--dpll_gmac_h12x2_ckti,divider-clock,?-Ddpll_gmac_h13x2_ckti,divider-clock,?-Ddpll_gmac_m3x2_ckti,divider-clock,-Dgmii_m_clk_divfixed-factor-clock-q|hdmi_clk2_divfixed-factor-clock%q|BBhdmi_div_clkfixed-factor-clock%q|HHl3_iclk_divti,divider-clock[l4_root_clk_divfixed-factor-clockq|video1_clk2_divfixed-factor-clock.q|@@video1_div_clkfixed-factor-clock.q|FFvideo2_clk2_divfixed-factor-clock/q|AAvideo2_div_clkfixed-factor-clock/q|GGipu1_gfclk_mux ti,mux-clock 0 mcasp1_ahclkr_mux ti,mux-clock8123456789:;<=>Pmcasp1_ahclkx_mux ti,mux-clock8123456789:;<=>Pmcasp1_aux_gfclk_mux ti,mux-clock?@ABPtimer5_gfclk_mux ti,mux-clock0CD89:;<EFGHIXtimer6_gfclk_mux ti,mux-clock0CD89:;<EFGHI`timer7_gfclk_mux ti,mux-clock0CD89:;<EFGHIhtimer8_gfclk_mux ti,mux-clock0CD89:;<EFGHIpuart6_gfclk_mux ti,mux-clockJKdummy_ck fixed-clockclockdomainscm_core@8000ti,dra7-cm-core0clocksdpll_pcie_ref_ckti,omap4-dpll-clock  LLdpll_pcie_ref_m2ldo_ckti,divider-clockL-DMMapll_pcie_in_clk_mux@4ae06118 ti,mux-clockMNOOapll_pcie_ckti,dra7-apll-clockOL PPoptfclk_pciephy1_32khz@4a0093b0ti,gate-clockDoptfclk_pciephy2_32khz@4a0093b8ti,gate-clockDoptfclk_pciephy_div@4a00821cti,divider-clockPQQoptfclk_pciephy1_clk@4a0093b0ti,gate-clockP optfclk_pciephy2_clk@4a0093b8ti,gate-clockP optfclk_pciephy1_div_clk@4a0093b0ti,gate-clockQ optfclk_pciephy2_div_clk@4a0093b8ti,gate-clockQ apll_pcie_clkvcoldofixed-factor-clockPq|apll_pcie_clkvcoldo_divfixed-factor-clockPq|apll_pcie_m2_ckfixed-factor-clockPq|dpll_per_byp_mux ti,mux-clock RLSSdpll_per_ckti,omap4-dpll-clock S@DLHTTdpll_per_m2_ckti,divider-clockTP-DUUfunc_96m_aon_dclk_divfixed-factor-clockUq|dpll_usb_byp_mux ti,mux-clock VWWdpll_usb_ckti,omap4-dpll-j-type-clock WXXdpll_usb_m2_ckti,divider-clockX-D[[dpll_pcie_ref_m2_ckti,divider-clockL-Ddpll_per_x2_ckti,omap4-dpll-x2-clockTYYdpll_per_h11x2_ckti,divider-clockY?X-DZZdpll_per_h12x2_ckti,divider-clockY?\-D^^dpll_per_h13x2_ckti,divider-clockY?`-Doodpll_per_h14x2_ckti,divider-clockY?d-Dggdpll_per_m2x2_ckti,divider-clockYP-DKKdpll_usb_clkdcoldofixed-factor-clockXq|]]func_128m_clkfixed-factor-clockZq|jjfunc_12m_fclkfixed-factor-clockKq|func_24m_clkfixed-factor-clockUq|33func_48m_fclkfixed-factor-clockKq|JJfunc_96m_fclkfixed-factor-clockKq|l3init_60m_fclkti,divider-clock[clkout2_clkti,gate-clock\l3init_960m_gfclkti,gate-clock]bbdss_32khz_clkti,gate-clockD  dss_48mhz_clkti,gate-clockJ  dss_dss_clkti,gate-clock^ dss_hdmi_clkti,gate-clock_  dss_video1_clkti,gate-clock`  dss_video2_clkti,gate-clocka  gpio2_dbclkti,gate-clockD`gpio3_dbclkti,gate-clockDhgpio4_dbclkti,gate-clockDpgpio5_dbclkti,gate-clockDxgpio6_dbclkti,gate-clockDgpio7_dbclkti,gate-clockDgpio8_dbclkti,gate-clockDmmc1_clk32kti,gate-clockD(mmc2_clk32kti,gate-clockD0mmc3_clk32kti,gate-clockD mmc4_clk32kti,gate-clockD(sata_ref_clkti,gate-clock usb_otg_ss1_refclk960mti,gate-clockbusb_otg_ss2_refclk960mti,gate-clockb@usb_phy1_always_on_clk32kti,gate-clockD@usb_phy2_always_on_clk32kti,gate-clockDusb_phy3_always_on_clk32kti,gate-clockDatl_dpll_clk_mux ti,mux-clockD./% ddatl_gfclk_mux ti,mux-clock cd gmac_gmii_ref_clk_divti,divider-clockegmac_rft_clk_mux ti,mux-clock./c%gpu_core_gclk_mux ti,mux-clock fgh gpu_hyd_gclk_mux ti,mux-clock fgh l3instr_ts_gclk_divti,divider-clockiP  mcasp2_ahclkr_mux ti,mux-clock8123456789:;<=>`mcasp2_ahclkx_mux ti,mux-clock8123456789:;<=>`mcasp2_aux_gfclk_mux ti,mux-clock?@AB`mcasp3_ahclkx_mux ti,mux-clock8123456789:;<=>hmcasp3_aux_gfclk_mux ti,mux-clock?@ABhmcasp4_ahclkx_mux ti,mux-clock8123456789:;<=>mcasp4_aux_gfclk_mux ti,mux-clock?@ABmcasp5_ahclkx_mux ti,mux-clock8123456789:;<=>xmcasp5_aux_gfclk_mux ti,mux-clock?@ABxmcasp6_ahclkx_mux ti,mux-clock8123456789:;<=>mcasp6_aux_gfclk_mux ti,mux-clock?@ABmcasp7_ahclkx_mux ti,mux-clock8123456789:;<=>mcasp7_aux_gfclk_mux ti,mux-clock?@ABmcasp8_ahclk_mux ti,mux-clock8123456789:;<=>mcasp8_aux_gfclk_mux ti,mux-clock?@ABmmc1_fclk_mux ti,mux-clockjK(kkmmc1_fclk_divti,divider-clockk([mmc2_fclk_mux ti,mux-clockjK0llmmc2_fclk_divti,divider-clockl0[mmc3_gfclk_mux ti,mux-clockJK mmmmc3_gfclk_divti,divider-clockm [mmc4_gfclk_mux ti,mux-clockJK(nnmmc4_gfclk_divti,divider-clockn([qspi_gfclk_mux ti,mux-clockjo8ppqspi_gfclk_divti,divider-clockp8[timer10_gfclk_mux ti,mux-clock,CD89:;<EFGH(timer11_gfclk_mux ti,mux-clock,CD89:;<EFGH0timer13_gfclk_mux ti,mux-clock,CD89:;<EFGHtimer14_gfclk_mux ti,mux-clock,CD89:;<EFGHtimer15_gfclk_mux ti,mux-clock,CD89:;<EFGHtimer16_gfclk_mux ti,mux-clock,CD89:;<EFGH0timer2_gfclk_mux ti,mux-clock,CD89:;<EFGH8timer3_gfclk_mux ti,mux-clock,CD89:;<EFGH@timer4_gfclk_mux ti,mux-clock,CD89:;<EFGHHtimer9_gfclk_mux ti,mux-clock,CD89:;<EFGHPuart1_gfclk_mux ti,mux-clockJK@uart2_gfclk_mux ti,mux-clockJKHuart3_gfclk_mux ti,mux-clockJKPuart4_gfclk_mux ti,mux-clockJKXuart5_gfclk_mux ti,mux-clockJKpuart7_gfclk_mux ti,mux-clockJKuart8_gfclk_mux ti,mux-clockJKuart9_gfclk_mux ti,mux-clockJKvip1_gclk_mux ti,mux-clockq vip2_gclk_mux ti,mux-clockq(vip3_gclk_mux ti,mux-clockq0clockdomainscoreaon_clkdmti,clockdomainXl4@4ae00000ti,dra7-l4-wkupsimple-bus /Jcounter@4000ti,omap-counter32k@@ %counter_32kprm@6000 ti,dra7-prm`0 clockssys_clkin1 ti,mux-clockrstuvwx-  abe_dpll_sys_clk_mux ti,mux-clock 8yyabe_dpll_bypass_clk_mux ti,mux-clockyDabe_dpll_clk_mux ti,mux-clockyD abe_24m_fclkti,divider-clock 11aess_fclkti,divider-clockzx{{abe_giclk_divti,divider-clock{tEEabe_lp_clk_divti,divider-clock  abe_sys_clk_divti,divider-clock  22adc_gfclk_mux ti,mux-clock  8Dsys_clk1_dclk_divti,divider-clock @[sys_clk2_dclk_divti,divider-clock8@[per_abe_x1_dclk_divti,divider-clockc@[dsp_gclk_divti,divider-clock|@[gpu_dclkti,divider-clockh@[emif_phy_dclk_divti,divider-clock}@[gmac_250m_dclk_divti,divider-clocke@[l3init_480m_dclk_divti,divider-clock[@[usb_otg_dclk_divti,divider-clock~@[sata_dclk_divti,divider-clock @[pcie2_dclk_divti,divider-clock@[pcie_dclk_divti,divider-clock@[emu_dclk_divti,divider-clock @[secure_32k_dclk_divti,divider-clock@[clkoutmux0_clk_mux ti,mux-clockXXIIclkoutmux1_clk_mux ti,mux-clockX\clkoutmux2_clk_mux ti,mux-clockX`\\custefuse_sys_gfclk_divfixed-factor-clock q|eve_clk ti,mux-clock)hdmi_dpll_clk_mux ti,mux-clock 8d__mlb_clkti,divider-clock@4[==mlbp_clkti,divider-clock@0[>>per_abe_x1_gfclk2_divti,divider-clockc@8[??timer_sys_clk_divti,divider-clock DCCvideo1_dpll_clk_mux ti,mux-clock 8h``video2_dpll_clk_mux ti,mux-clock 8laawkupaon_iclk_mux ti,mux-clock iigpio1_dbclkti,gate-clockD8dcan1_sys_clk_mux ti,mux-clock 8timer1_gfclk_mux ti,mux-clock,CD89:;<EFGH@uart10_gfclk_mux ti,mux-clockJKclockdomainsaxi@0 simple-bus/QQ0 pcie@51000000 ti,dra7-pcieQ Q L rc_dbicsti_confconfigpci0/0 00%pcie1 pcie-phy0`interrupt-controlleraxi@1 simple-bus/QQ00 disabledpcie@51000000 ti,dra7-pcieQ Q L rc_dbicsti_confconfigcdpci0/0000%pcie2 pcie-phy0`interrupt-controllerbandgap@4a0021e00J! J#, J#,J#htxrxokay.default;GW aj qmmc@480b4000ti,omap4-hsmmcH @ Q%mmc2c/0htxrxokaydefault;Wxj qmmc@480ad000ti,omap4-hsmmcH  Y%mmc3cMNhtxrx disabledmmc@480d1000ti,omap4-hsmmcH  [%mmc4c9:htxrx disabledmmu@40d01000ti,dra7-dsp-iommu@  %mmu0_dsp1 disabledmmu@40d02000ti,dra7-dsp-iommu@   %mmu1_dsp1 disabledmmu@58882000ti,dra7-iommuX   %mmu_ipu1 disabledmmu@55082000ti,dra7-iommuU   %mmu_ipu2 disabledregulator-abb-mpu ti,abb-v3Qabb_mpu 2(J}J}J`J; JXDsetup-addresscontrol-addressint-addressefuse-addressldo-addressH&,@vregulator-abb-ivahd ti,abb-v3 Qabb_ivahd 2(J~4J~$J`J% J$pDsetup-addresscontrol-addressint-addressefuse-addressldo-address@H&0regulator-abb-dspeve ti,abb-v3 Qabb_dspeve 2(J~0J~ J`J% J$lDsetup-addresscontrol-addressint-addressefuse-addressldo-address H&0regulator-abb-gpu ti,abb-v3Qabb_gpu 2(J}J}J`J; JTDsetup-addresscontrol-addressint-addressefuse-addressldo-addressH&vspi@48098000ti,omap4-mcspiH  <%mcspi12@c#$%&'()* htx0rx0tx1rx1tx2rx2tx3rx3 disabledspi@4809a000ti,omap4-mcspiH  =%mcspi22 c+,-.htx0rx0tx1rx1 disabledspi@480b8000ti,omap4-mcspiH  V%mcspi32chtx0rx0 disabledspi@480ba000ti,omap4-mcspiH  +%mcspi42cFGhtx0rx0 disabledqspi@4b300000ti,dra7xxx-qspiK0\qspi_baseqspi_mmap@X%qspiSfck9 Wokaydefault_lm25p80@0 s25fl256s1_lqpartition@0 QSPI.SPLpartition@1QSPI.SPL.backup1partition@2QSPI.SPL.backup2partition@3QSPI.SPL.backup3partition@4 QSPI.u-bootpartition@5QSPI.u-boot-spl-ospartition@6QSPI.u-boot-envpartition@7QSPI.u-boot-env.backup1partition@8 QSPI.kernelpartition@9QSPI.file-systembcontrol-phy@4a002374ti,control-phy-pipe3J#tpower Ssysclkocp2scp@4a090000ti,omap-ocp2scp/J  %ocp2scp3phy@4A096000ti,phy-pipe3-sataJ `J ddJ h@phy_rxphy_txpll_ctrl Ssysclkrefclkpciephy@4a094000ti,phy-pipe3-pcieJ @J Ddphy_rxphy_txLMQ4Sdpll_refdpll_ref_m2wkupclkrefclkdiv-clkphy-divpciephy@4a095000ti,phy-pipe3-pcieJ PJ Tdphy_rxphy_txLMQ4Sdpll_refdpll_ref_m2wkupclkrefclkdiv-clkphy-div disabledsata@4a141100snps,dwc-ahciJJ 1 sata-phy%satacontrol-phy@0x4a003c40ti,control-phy-pcieJ<@J<J<4powercontrol_smapcie_pcs Ssysclkcontrol-pcie@0x4a003c44ti,control-phy-pcieJ8c U @V"atl2 j nmcasp@48468000ti,dra7-mcasp-audio%mcasp3HF mputxrxchtxrx Sfckahclkxokaydefaultsleep r . >5 |  crossbar@4a002a48ti,irq-crossbarJ*H0&      ethernet@48484000ti,dra7-cpswti,cpsw%gmac" Sfckcpts      )@ 2  > E R bHH@HHR. s0NOPQ/Jokaydefaultsleep r ~mdio@48485000ti,davinci_mdio %davinci_mdio B@HHPdefaultsleep rslave@48480200   rgmiislave@48480300 cpsw-phy-sel@4a002554ti,dra7xx-cpsw-phy-selJ%T gmii-selcan@481cc000ti,dra7-d_can%dcan1J  X okdefaultsleepactive r can@481d0000ti,dra7-d_can%dcan2HH  X   disableddss@58000000 ti,dra7-dssok %dss_core 8/XX@TXC dsspll1_clkctrlpll1Sfckvideo1_clk dispc@58001000ti,dra7-dispcX  %dss_dispcSfck 4encoder@58060000 ti,dra7-hdmi XXXXwppllphycore `ok %dss_hdmi Sfcksys_clk defaultportendpoint thermal-zonescpu_thermal  & 4tripscpu_alert D Ppassivecpu_crit DH P criticalcooling-mapsmap0 [ `gpu_thermal  & 4tripsgpu_crit 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#address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2i2c3i2c4serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9ethernet0ethernet1d_can0d_can1spi0display0device_typereginterruptsinterrupt-controller#interrupt-cellslinux,phandleti,hwmodsrangesinterrupts-extendedsysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsclocksti,bit-shiftpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinsclock-frequencyti,max-divti,autoidle-shiftti,index-starts-at-oneti,invert-autoidle-bitti,index-power-of-twoclock-multclock-divti,dividersti,set-rate-parentreg-namesnum-lanesphysphy-namesinterrupt-map-maskinterrupt-mapstatus#thermal-sensor-cells#dma-cellsdma-channelsdma-requeststi,dma-safe-mapdma-mastersgpio-controller#gpio-cellsdmasdma-names#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,timer-alwon#hwlock-cellspinctrl-namespinctrl-0ti,system-power-controllerregulator-always-onregulator-boot-onregulator-allow-bypasswakeup-sourceti,palmas-long-press-secondslines-initial-states#sound-dai-cellsadc-settle-msai3x-micbias-vgAVDD-supplyIOVDD-supplyDRVDD-supplyDVDD-supplygpio-hoggpiosoutput-lowline-nameti,dual-voltti,needs-special-resetpbias-supplyvmmc-supplyvmmc_aux-supplybus-widthcd-gpiosmax-frequencyti,non-removable#iommu-cellsti,syscon-mmuconfigti,iommu-bus-err-backti,settling-timeti,clock-cyclesti,tranxdone-status-maskti,ldovbb-override-maskti,ldovbb-vset-maskti,abb_infoti,spi-num-cssyscon-chipselectsclock-namesspi-max-frequencyspi-tx-bus-widthspi-rx-bus-widthspi-cpolspi-cphalabelctrl-modulesyscon-pllreset#phy-cellsphy-supplyutmi-modeextconinterrupt-namestx-fifo-resizemaximum-speeddr_modesnps,dis_u3_susphy_quirksnps,dis_u2_susphy_quirkgpmc,num-csgpmc,num-waitpinsti,nand-ecc-optti,elm-idnand-bus-widthgpmc,device-widthgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,access-nsgpmc,wr-access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,clk-activation-nsgpmc,wait-monitoring-nsgpmc,wr-data-mux-bus-nsti,provided-clocksassigned-clocksassigned-clock-parentsassigned-clock-ratesbwsawspinctrl-1op-modetdm-slotsserial-dirti,max-irqsti,max-crossbar-sourcesti,reg-sizeti,irqs-reservedti,irqs-skipti,irqs-safe-mapcpdma_channelsale_entriesbd_ram_sizeno_bd_ramrx_descsmac_controlslavesactive_slavecpts_clock_multcpts_clock_shiftti,no-idlemode-gpiosbus_freqmac-addressphy_idphy-modesyscon-raminitpinctrl-2syscon-pll-ctrlvdda_video-supplysyscon-polvdda-supplyremote-endpointpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicecooling-min-levelcooling-max-level#cooling-cellsvin-supplyenable-active-highgpioid-gpiosimple-audio-card,namesimple-audio-card,widgetssimple-audio-card,routingsimple-audio-card,formatsimple-audio-card,bitclock-mastersimple-audio-card,frame-mastersimple-audio-card,bitclock-inversionsound-daisystem-clock-frequency