0{8&( s%;compulab,cl-som-am57xti,am5728ti,dra742ti,dra74ti,dra7&7CompuLab CL-SOM-AM57xchosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/i2c@4807a000Q/ocp/i2c@4807c000V/ocp/serial@4806a000^/ocp/serial@4806c000f/ocp/serial@48020000n/ocp/serial@4806e000v/ocp/serial@48066000~/ocp/serial@48068000/ocp/serial@48420000/ocp/serial@48422000/ocp/serial@48424000/ocp/serial@4ae2b000&/ocp/ethernet@48484000/slave@48480200&/ocp/ethernet@48484000/slave@48480300/ocp/can@481cc000/ocp/can@481d0000/ocp/qspi@4b300000memorymemory timerarm,armv7-timer0   &interrupt-controller@48211000arm,cortex-a15-gic@H!H! H!@ H!`   &interrupt-controller@48281000&ti,omap5-wugen-mputi,omap4-wugen-mpuH(&socti,omap-inframpu ti,omap5-mpumpuocpti,dra7-l3-nocsimple-bus&l3_main_1l3_main_2 DE - l4@4a000000ti,dra7-l4-cfgsimple-bus &J"scm@2000ti,dra7-scm-coresimple-bus  & scm_conf@0sysconsimple-bus &pbias_regulatorti,pbias-dra7ti,pbias-omapApbias_mmc_omap5Hpbias_mmc_omap5Ww@o-clocksdss_deshdcp_clkti,gate-clockXehrpwm0_tbclkti,gate-clockXehrpwm1_tbclkti,gate-clockXehrpwm2_tbclkti,gate-clockXsys_32k_ck ti,mux-clockGGpinmux@1400ti,dra7-padconfpinctrl-singleh ?leds_pins_default|i2c1_pins_defaulti2c3_pins_default  i2c4_pins_default  tps659038_pins_defaultmmc2_pins_defaultPpinmux_qspi1_pins0tcpsw_pins_defaultPTX\`dhlptx|cpsw_pins_sleepPTX\`dhlptx|davinci_mdio_pins_defaultdavinci_mdio_pins_sleeppinmux_ads7846_pinsdmcasp3_pins_default $(,0mcasp3_pins_sleep $(,0scm_conf@1c04syscon scm_conf@1c24syscon$$cm_core_aon@5000ti,dra7-cm-core-aonP clocksatl_clkin0_ckti,dra7-atl-clock ::atl_clkin1_ckti,dra7-atl-clock 99atl_clkin2_ckti,dra7-atl-clock 88atl_clkin3_ckti,dra7-atl-clock 77hdmi_clkin_ck fixed-clock((mlb_clkin_ck fixed-clockmlbp_clkin_ck fixed-clockpciesref_acs_clk_ck fixed-clockQQref_clkin0_ck fixed-clock<<ref_clkin1_ck fixed-clock==ref_clkin2_ck fixed-clock>>ref_clkin3_ck fixed-clock??rmii_clk_ck fixed-clocksdvenc_clkin_ck fixed-clocksecure_32k_clk_src_ck fixed-clocksys_clk32_crystal_ck fixed-clocksys_clk32_pseudo_ckfixed-factor-clock bvirt_12000000_ck fixed-clockuuvirt_13000000_ck fixed-clock]@virt_16800000_ck fixed-clockYwwvirt_19200000_ck fixed-clock$xxvirt_20000000_ck fixed-clock1-vvvirt_26000000_ck fixed-clockyyvirt_27000000_ck fixed-clockzzvirt_38400000_ck fixed-clockI{{sys_clkin2 fixed-clockX;;usb_otg_clkin_ck fixed-clockvideo1_clkin_ck fixed-clock11video1_m2_clkin_ck fixed-clock''video2_clkin_ck fixed-clock22video2_m2_clkin_ck fixed-clock&&dpll_abe_ckti,omap4-dpll-m4xen-clock   dpll_abe_x2_ckti,omap4-dpll-x2-clock dpll_abe_m2x2_ckti,divider-clock'9Pabe_clkti,divider-clockg}}dpll_abe_m2_ckti,divider-clock '9Pffdpll_abe_m3x2_ckti,divider-clock'9Pdpll_core_byp_mux ti,mux-clock ,dpll_core_ckti,omap4-dpll-core-clock  $,(dpll_core_x2_ckti,omap4-dpll-x2-clockdpll_core_h12x2_ckti,divider-clock?'<9Pmpu_dpll_hs_clk_divfixed-factor-clockdpll_mpu_ckti,omap5-mpu-dpll-clock `dlhdpll_mpu_m2_ckti,divider-clock'p9Pmpu_dclk_divfixed-factor-clockdsp_dpll_hs_clk_divfixed-factor-clockdpll_dsp_byp_mux ti,mux-clock @dpll_dsp_ckti,omap4-dpll-clock 48@<dpll_dsp_m2_ckti,divider-clock'D9Piva_dpll_hs_clk_divfixed-factor-clockdpll_iva_byp_mux ti,mux-clock dpll_iva_ckti,omap4-dpll-clock dpll_iva_m2_ckti,divider-clock'9Piva_dclkfixed-factor-clockdpll_gpu_byp_mux ti,mux-clock dpll_gpu_ckti,omap4-dpll-clock   dpll_gpu_m2_ckti,divider-clock '9Pkkdpll_core_m2_ckti,divider-clock'09P!!core_dpll_out_dclk_divfixed-factor-clock!dpll_ddr_byp_mux ti,mux-clock ""dpll_ddr_ckti,omap4-dpll-clock "##dpll_ddr_m2_ckti,divider-clock#' 9Pdpll_gmac_byp_mux ti,mux-clock $$dpll_gmac_ckti,omap4-dpll-clock $%%dpll_gmac_m2_ckti,divider-clock%'9Phhvideo2_dclk_divfixed-factor-clock&video1_dclk_divfixed-factor-clock'hdmi_dclk_divfixed-factor-clock(per_dpll_hs_clk_divfixed-factor-clockUUusb_dpll_hs_clk_divfixed-factor-clockYYeve_dpll_hs_clk_divfixed-factor-clock))dpll_eve_byp_mux ti,mux-clock )**dpll_eve_ckti,omap4-dpll-clock *++dpll_eve_m2_ckti,divider-clock+'9P,,eve_dclk_divfixed-factor-clock,dpll_core_h13x2_ckti,divider-clock?'@9Pdpll_core_h14x2_ckti,divider-clock?'D9Piidpll_core_h22x2_ckti,divider-clock?'T9P33dpll_core_h23x2_ckti,divider-clock?'X9Pttdpll_core_h24x2_ckti,divider-clock?'\9Pdpll_ddr_x2_ckti,omap4-dpll-x2-clock#--dpll_ddr_h11x2_ckti,divider-clock-?'(9Pdpll_dsp_x2_ckti,omap4-dpll-x2-clock..dpll_dsp_m3x2_ckti,divider-clock.'H9Pdpll_gmac_x2_ckti,omap4-dpll-x2-clock%//dpll_gmac_h11x2_ckti,divider-clock/?'9P00dpll_gmac_h12x2_ckti,divider-clock/?'9Pdpll_gmac_h13x2_ckti,divider-clock/?'9Pdpll_gmac_m3x2_ckti,divider-clock/'9Pgmii_m_clk_divfixed-factor-clock0hdmi_clk2_divfixed-factor-clock(EEhdmi_div_clkfixed-factor-clock(KKl3_iclk_divti,divider-clockgl4_root_clk_divfixed-factor-clockvideo1_clk2_divfixed-factor-clock1CCvideo1_div_clkfixed-factor-clock1IIvideo2_clk2_divfixed-factor-clock2DDvideo2_div_clkfixed-factor-clock2JJipu1_gfclk_mux ti,mux-clock3 mcasp1_ahclkr_mux ti,mux-clock8456789:;<=>?@APmcasp1_ahclkx_mux ti,mux-clock8456789:;<=>?@APmcasp1_aux_gfclk_mux ti,mux-clockBCDEPtimer5_gfclk_mux ti,mux-clock0FG;<=>?HIJKLXtimer6_gfclk_mux ti,mux-clock0FG;<=>?HIJKL`timer7_gfclk_mux ti,mux-clock0FG;<=>?HIJKLhtimer8_gfclk_mux ti,mux-clock0FG;<=>?HIJKLpuart6_gfclk_mux ti,mux-clockMNdummy_ck fixed-clockclockdomainscm_core@8000ti,dra7-cm-core0clocksdpll_pcie_ref_ckti,omap4-dpll-clock  OOdpll_pcie_ref_m2ldo_ckti,divider-clockO'9PPPapll_pcie_in_clk_mux@4ae06118 ti,mux-clockPQRRapll_pcie_ckti,dra7-apll-clockRO SSoptfclk_pciephy1_32khz@4a0093b0ti,gate-clockGoptfclk_pciephy2_32khz@4a0093b8ti,gate-clockGoptfclk_pciephy_div@4a00821cti,divider-clockS}TToptfclk_pciephy1_clk@4a0093b0ti,gate-clockS optfclk_pciephy2_clk@4a0093b8ti,gate-clockS optfclk_pciephy1_div_clk@4a0093b0ti,gate-clockT optfclk_pciephy2_div_clk@4a0093b8ti,gate-clockT apll_pcie_clkvcoldofixed-factor-clockSapll_pcie_clkvcoldo_divfixed-factor-clockSapll_pcie_m2_ckfixed-factor-clockSdpll_per_byp_mux ti,mux-clock ULVVdpll_per_ckti,omap4-dpll-clock V@DLHWWdpll_per_m2_ckti,divider-clockW'P9PXXfunc_96m_aon_dclk_divfixed-factor-clockXdpll_usb_byp_mux ti,mux-clock YZZdpll_usb_ckti,omap4-dpll-j-type-clock Z[[dpll_usb_m2_ckti,divider-clock['9P^^dpll_pcie_ref_m2_ckti,divider-clockO'9Pdpll_per_x2_ckti,omap4-dpll-x2-clockW\\dpll_per_h11x2_ckti,divider-clock\?'X9P]]dpll_per_h12x2_ckti,divider-clock\?'\9Paadpll_per_h13x2_ckti,divider-clock\?'`9Prrdpll_per_h14x2_ckti,divider-clock\?'d9Pjjdpll_per_m2x2_ckti,divider-clock\'P9PNNdpll_usb_clkdcoldofixed-factor-clock[``func_128m_clkfixed-factor-clock]mmfunc_12m_fclkfixed-factor-clockNfunc_24m_clkfixed-factor-clockX66func_48m_fclkfixed-factor-clockNMMfunc_96m_fclkfixed-factor-clockNl3init_60m_fclkti,divider-clock^}clkout2_clkti,gate-clock_l3init_960m_gfclkti,gate-clock`eedss_32khz_clkti,gate-clockG  dss_48mhz_clkti,gate-clockM  dss_dss_clkti,gate-clocka dss_hdmi_clkti,gate-clockb  dss_video1_clkti,gate-clockc  dss_video2_clkti,gate-clockd  gpio2_dbclkti,gate-clockG`gpio3_dbclkti,gate-clockGhgpio4_dbclkti,gate-clockGpgpio5_dbclkti,gate-clockGxgpio6_dbclkti,gate-clockGgpio7_dbclkti,gate-clockGgpio8_dbclkti,gate-clockGmmc1_clk32kti,gate-clockG(mmc2_clk32kti,gate-clockG0mmc3_clk32kti,gate-clockG mmc4_clk32kti,gate-clockG(sata_ref_clkti,gate-clock usb_otg_ss1_refclk960mti,gate-clockeusb_otg_ss2_refclk960mti,gate-clocke@usb_phy1_always_on_clk32kti,gate-clockG@usb_phy2_always_on_clk32kti,gate-clockGusb_phy3_always_on_clk32kti,gate-clockGatl_dpll_clk_mux ti,mux-clockG12( ggatl_gfclk_mux ti,mux-clock fg   gmac_gmii_ref_clk_divti,divider-clockh}gmac_rft_clk_mux ti,mux-clock12f(gpu_core_gclk_mux ti,mux-clock ijk gpu_hyd_gclk_mux ti,mux-clock ijk l3instr_ts_gclk_divti,divider-clocklP } mcasp2_ahclkr_mux ti,mux-clock8456789:;<=>?@A`mcasp2_ahclkx_mux ti,mux-clock8456789:;<=>?@A`mcasp2_aux_gfclk_mux ti,mux-clockBCDE`mcasp3_ahclkx_mux ti,mux-clock8456789:;<=>?@Ahmcasp3_aux_gfclk_mux ti,mux-clockBCDEhmcasp4_ahclkx_mux ti,mux-clock8456789:;<=>?@Amcasp4_aux_gfclk_mux ti,mux-clockBCDEmcasp5_ahclkx_mux ti,mux-clock8456789:;<=>?@Axmcasp5_aux_gfclk_mux ti,mux-clockBCDExmcasp6_ahclkx_mux ti,mux-clock8456789:;<=>?@Amcasp6_aux_gfclk_mux ti,mux-clockBCDEmcasp7_ahclkx_mux ti,mux-clock8456789:;<=>?@Amcasp7_aux_gfclk_mux ti,mux-clockBCDEmcasp8_ahclk_mux ti,mux-clock8456789:;<=>?@Amcasp8_aux_gfclk_mux ti,mux-clockBCDEmmc1_fclk_mux ti,mux-clockmN(nnmmc1_fclk_divti,divider-clockn(gmmc2_fclk_mux ti,mux-clockmN0oommc2_fclk_divti,divider-clocko0gmmc3_gfclk_mux ti,mux-clockMN ppmmc3_gfclk_divti,divider-clockp gmmc4_gfclk_mux ti,mux-clockMN(qqmmc4_gfclk_divti,divider-clockq(gqspi_gfclk_mux ti,mux-clockmr8ssqspi_gfclk_divti,divider-clocks8gtimer10_gfclk_mux ti,mux-clock,FG;<=>?HIJK(timer11_gfclk_mux ti,mux-clock,FG;<=>?HIJK0timer13_gfclk_mux ti,mux-clock,FG;<=>?HIJKtimer14_gfclk_mux ti,mux-clock,FG;<=>?HIJKtimer15_gfclk_mux ti,mux-clock,FG;<=>?HIJKtimer16_gfclk_mux ti,mux-clock,FG;<=>?HIJK0timer2_gfclk_mux ti,mux-clock,FG;<=>?HIJK8timer3_gfclk_mux ti,mux-clock,FG;<=>?HIJK@timer4_gfclk_mux ti,mux-clock,FG;<=>?HIJKHtimer9_gfclk_mux ti,mux-clock,FG;<=>?HIJKPuart1_gfclk_mux ti,mux-clockMN@uart2_gfclk_mux ti,mux-clockMNHuart3_gfclk_mux ti,mux-clockMNPuart4_gfclk_mux ti,mux-clockMNXuart5_gfclk_mux ti,mux-clockMNpuart7_gfclk_mux ti,mux-clockMNuart8_gfclk_mux ti,mux-clockMNuart9_gfclk_mux ti,mux-clockMNvip1_gclk_mux ti,mux-clockt vip2_gclk_mux ti,mux-clockt(vip3_gclk_mux ti,mux-clockt0clockdomainscoreaon_clkdmti,clockdomain[l4@4ae00000ti,dra7-l4-wkupsimple-bus &Jcounter@4000ti,omap-counter32k@@ counter_32kprm@6000 ti,dra7-prm`0 clockssys_clkin1 ti,mux-clockuvwxyz{9  abe_dpll_sys_clk_mux ti,mux-clock ;||abe_dpll_bypass_clk_mux ti,mux-clock|G  abe_dpll_clk_mux ti,mux-clock|G   abe_24m_fclkti,divider-clock}44aess_fclkti,divider-clock}x~~abe_giclk_divti,divider-clock~tHHabe_lp_clk_divti,divider-clock} abe_sys_clk_divti,divider-clock  55adc_gfclk_mux ti,mux-clock  ;Gsys_clk1_dclk_divti,divider-clock @gsys_clk2_dclk_divti,divider-clock;@gper_abe_x1_dclk_divti,divider-clockf@gdsp_gclk_divti,divider-clock@ggpu_dclkti,divider-clockk@gemif_phy_dclk_divti,divider-clock@ggmac_250m_dclk_divti,divider-clockh@gl3init_480m_dclk_divti,divider-clock^@gusb_otg_dclk_divti,divider-clock@gsata_dclk_divti,divider-clock @gpcie2_dclk_divti,divider-clock@gpcie_dclk_divti,divider-clock@gemu_dclk_divti,divider-clock @gsecure_32k_dclk_divti,divider-clock@gclkoutmux0_clk_mux ti,mux-clockXXLLclkoutmux1_clk_mux ti,mux-clockX\clkoutmux2_clk_mux ti,mux-clockX`__custefuse_sys_gfclk_divfixed-factor-clock eve_clk ti,mux-clock,hdmi_dpll_clk_mux ti,mux-clock ;dbbmlb_clkti,divider-clock@4g@@mlbp_clkti,divider-clock@0gAAper_abe_x1_gfclk2_divti,divider-clockf@8gBBtimer_sys_clk_divti,divider-clock DFFvideo1_dpll_clk_mux ti,mux-clock ;hccvideo2_dpll_clk_mux ti,mux-clock ;lddwkupaon_iclk_mux ti,mux-clock llgpio1_dbclkti,gate-clockG8dcan1_sys_clk_mux ti,mux-clock ;timer1_gfclk_mux ti,mux-clock,FG;<=>?HIJK@uart10_gfclk_mux ti,mux-clockMNclockdomainsaxi@0 simple-bus&QQ0 pcie@51000000 ti,dra7-pcieQ Q L rc_dbicsti_confconfigpci0&0 00pcie1 pcie-phy0`interrupt-controlleraxi@1 simple-bus&QQ00 disabledpcie@51000000 ti,dra7-pcieQ Q L rc_dbicsti_confconfigcdpci0&0000pcie2 pcie-phy0`interrupt-controllerbandgap@4a0021e00J! J#, J#,J#Ngpio@48055000ti,omap4-gpioHP gpio2>NokayZgpio@48057000ti,omap4-gpioHp gpio3>NokayZgpio@48059000ti,omap4-gpioH gpio4>Ngpio@4805b000ti,omap4-gpioH gpio5>Ngpio@4805d000ti,omap4-gpioH gpio6>Ngpio@48051000ti,omap4-gpioH gpio7>Ngpio@48053000ti,omap4-gpioH0 tgpio8>Nserial@4806a000ti,dra742-uartti,omap4-uartH-Cuart1l disabledn12stxrxserial@4806c000ti,dra742-uartti,omap4-uartH Duart2l disabledn34stxrxserial@48020000ti,dra742-uartti,omap4-uartH Euart3l disabledn56stxrxserial@4806e000ti,dra742-uartti,omap4-uartH Auart4l disabledn78stxrxserial@48066000ti,dra742-uartti,omap4-uartH` duart5l disabledn?@stxrxserial@48068000ti,dra742-uartti,omap4-uartH euart6l disablednOPstxrxserial@48420000ti,dra742-uartti,omap4-uartHB uart7l disabledserial@48422000ti,dra742-uartti,omap4-uartHB  uart8l disabledserial@48424000ti,dra742-uartti,omap4-uartHB@ uart9l disabledserial@4ae2b000ti,dra742-uartti,omap4-uartJ uart10l disabledmailbox@4a0f4000ti,omap4-mailboxJ@$ mailbox1} disabledmailbox@4883a000ti,omap4-mailboxH0 mailbox2}  disabledmailbox@4883c000ti,omap4-mailboxH0 mailbox3}  disabledmailbox@4883e000ti,omap4-mailboxH0 mailbox4}  disabledmailbox@48840000ti,omap4-mailboxH0 mailbox5} okaymbox_ipu1_ipc3x  okaymbox_dsp1_ipc3x  okaymailbox@48842000ti,omap4-mailboxH 0 mailbox6} okaymbox_ipu2_ipc3x  okaymbox_dsp2_ipc3x  okaymailbox@48844000ti,omap4-mailboxH@0 mailbox7}  disabledmailbox@48846000ti,omap4-mailboxH`0 mailbox8}  disabledmailbox@4885e000ti,omap4-mailboxH0     mailbox9}  disabledmailbox@48860000ti,omap4-mailboxH0  mailbox10}  disabledmailbox@48862000ti,omap4-mailboxH 0 mailbox11}  disabledmailbox@48864000ti,omap4-mailboxH@0 mailbox12}  disabledmailbox@48802000ti,omap4-mailboxH 0{|}~ mailbox13}  disabledtimer@4ae18000ti,omap5430-timerJ timer1timer@48032000ti,omap5430-timerH  !timer2timer@48034000ti,omap5430-timerH@ "timer3timer@48036000ti,omap5430-timerH` #timer4timer@48820000ti,omap5430-timerH $timer5timer@48822000ti,omap5430-timerH  %timer6timer@48824000ti,omap5430-timerH@ &timer7timer@48826000ti,omap5430-timerH` 'timer8timer@4803e000ti,omap5430-timerH (timer9timer@48086000ti,omap5430-timerH` )timer10timer@48088000ti,omap5430-timerH *timer11timer@48828000ti,omap5430-timerH Stimer13 disabledtimer@4882a000ti,omap5430-timerH Ttimer14 disabledtimer@4882c000ti,omap5430-timerH Utimer15 disabledtimer@4882e000ti,omap5430-timerH Vtimer16 disabledwdt@4ae14000 ti,omap3-wdtJ@ K wd_timer2spinlock@4a0f6000ti,omap4-hwspinlockJ` spinlockdmm@4e000000 ti,omap5-dmmN ldmmi2c@48070000 ti,omap4-i2cH 3i2c1okaydefaulti2c@48072000 ti,omap4-i2cH  4i2c2 disabledi2c@48060000 ti,omap4-i2cH 8i2c3okaydefaulti2c@4807a000 ti,omap4-i2cH 9i2c4okaydefaulttps659038@58 ti,tps659038X&defaulttps659038_pmicti,tps659038-pmicregulatorssmps12Hsmps12W Po'smps3Hsmps3W`o`'smps45Hsmps45W Po'smps6Hsmps6W Po'smps7Hsmps7W Po@'smps8Hsmps8W Po'smps9Hsmps9W2Zo2Z'ldo1Hldo1Ww@o2Z'ldo2Hldo2Ww@ow@'ldo3Hldo3Ww@ow@'ldo4Hldo4Ww@ow@'ldo9Hldo9Wo'ldolnHldolnWw@ow@'ldousbHldousbW2Zo2Z'tps659038_pwr_buttonti,palmas-pwrbutton&9G tps659038_gpioti,palmas-gpio>Nrtc@56emmicro,em3027Vatmel@50 atmel,24c08Pdwm8731@1am wlf,wm8731okayi2c@4807c000 ti,omap4-i2cH 7i2c5 disabledmmc@4809c000ti,omap4-hsmmcH  Nmmc1~n=>stxrx disabledmmc@480b4000ti,omap4-hsmmcH @ Qmmc2n/0stxrxokaydefaultmmc@480ad000ti,omap4-hsmmcH  Ymmc3nMNstxrx disabledmmc@480d1000ti,omap4-hsmmcH  [mmc4n9:stxrx disabledmmu@40d01000ti,dra7-dsp-iommu@  mmu0_dsp1 disabledmmu@40d02000ti,dra7-dsp-iommu@   mmu1_dsp1 disabledmmu@58882000ti,dra7-iommuX   mmu_ipu1 disabledmmu@55082000ti,dra7-iommuU   mmu_ipu2 disabledregulator-abb-mpu ti,abb-v3Habb_mpu $25(J}J}J`J; JXDsetup-addresscontrol-addressint-addressefuse-addressldo-addressE^vH,@vregulator-abb-ivahd ti,abb-v3 Habb_ivahd $25(J~4J~$J`J% J$pDsetup-addresscontrol-addressint-addressefuse-addressldo-addressE@^vH0regulator-abb-dspeve ti,abb-v3 Habb_dspeve $25(J~0J~ J`J% J$lDsetup-addresscontrol-addressint-addressefuse-addressldo-addressE ^vH0regulator-abb-gpu ti,abb-v3Habb_gpu $25(J}J}J`J; JTDsetup-addresscontrol-addressint-addressefuse-addressldo-addressE^vHvspi@48098000ti,omap4-mcspiH  <mcspi1@n#$%&'()* stx0rx0tx1rx1tx2rx2tx3rx3 disabledspi@4809a000ti,omap4-mcspiH  =mcspi2 n+,-.stx0rx0tx1rx1 disabledspi@480b8000ti,omap4-mcspiH  Vmcspi3nstx0rx0 disabledspi@480ba000ti,omap4-mcspiH  +mcspi4nFGstx0rx0 disabledqspi@4b300000ti,dra7xxx-qspiK0\qspi_baseqspi_mmapXqspifck Wokaydefaultlspi_flash@0spansion,m25p80jedec,spi-norlpartition@0uboot partition@c0000uboot environment partition@100000 reservedads7846@0default ti,ads7846`& '7G W9ocp2scp@4a090000ti,omap-ocp2scp&J  ocp2scp3phy@4A096000ti,phy-pipe3-sataJ `J ddJ h@phy_rxphy_txpll_ctrlgt sysclkrefclkxpciephy@4a094000ti,phy-pipe3-pcieJ @J Ddphy_rxphy_txgOPT ;dpll_refdpll_ref_m2wkupclkrefclkdiv-clkphy-divsysclkpciephy@4a095000ti,phy-pipe3-pcieJ PJ Tdphy_rxphy_txg OPT ;dpll_refdpll_ref_m2wkupclkrefclkdiv-clkphy-divsysclk disabledsata@4a141100snps,dwc-ahciJJ 1 sata-physataokayrtc@48838000ti,am3352-rtcHrtcssGocp2scp@4a080000ti,omap-ocp2scp&J  ocp2scp1phy@4a084000 ti,omap-usb2J@gwkupclkrefclkphy@4a085000 ti,dra7x-usb2-phy2ti,omap-usb2JPgtwkupclkrefclkphy@4a084400 ti,omap-usb3JDJHdJL@phy_rxphy_txpll_ctrlgp  wkupclksysclkrefclkomap_dwc3_1@48880000ti,dwc3 usb_otg_ss1H H&usb@48890000 snps,dwc3Hp$GGHperipheralhostotgusb2-phyusb3-phy super-speedhostomap_dwc3_2@488c0000ti,dwc3 usb_otg_ss2H W&usb@488d0000 snps,dwc3Hp$IIWperipheralhostotg usb2-phy high-speedhostomap_dwc3_3@48900000ti,dwc3 usb_otg_ss3H X& disabledusb@48910000 snps,dwc3Hp$XXXperipheralhostotg high-speedotgelm@48078000ti,am3352-elmH elm disabledgpmc@50000000ti,am3352-gpmcgpmcP|   disabledatl@4843c000 ti,dra7-atlHCatl):987 fck disabledmcasp@48468000ti,dra7-mcasp-audiomcasp3HF mputxrxnstxrx fckahclkxokaymdefaultsleep<FNXcrossbar@4a002a48ti,irq-crossbarJ*H0&co  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#address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2i2c3i2c4serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9ethernet0ethernet1d_can0d_can1spi0device_typereginterruptsinterrupt-controller#interrupt-cellslinux,phandleti,hwmodsrangesinterrupts-extendedsysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsclocksti,bit-shiftpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinsclock-frequencyclock-multclock-divti,max-divti,autoidle-shiftti,index-starts-at-oneti,invert-autoidle-bitti,index-power-of-twoti,dividersti,set-rate-parentreg-namesnum-lanesphysphy-namesinterrupt-map-maskinterrupt-mapstatus#thermal-sensor-cells#dma-cellsdma-channelsdma-requeststi,dma-safe-mapdma-mastersgpio-controller#gpio-cellsti,no-reset-on-initdmasdma-names#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,timer-alwon#hwlock-cellspinctrl-namespinctrl-0ti,system-power-controllerregulator-always-onregulator-boot-onwakeup-sourceti,palmas-long-press-secondspagesize#sound-dai-cellsti,dual-voltti,needs-special-resetpbias-supplyvmmc-supplybus-widthti,non-removablecap-mmc-dual-data-rate#iommu-cellsti,syscon-mmuconfigti,iommu-bus-err-backti,settling-timeti,clock-cyclesti,tranxdone-status-maskti,ldovbb-override-maskti,ldovbb-vset-maskti,abb_infoti,spi-num-cssyscon-chipselectsclock-namesspi-max-frequencylabelvcc-supplypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,debounce-maxti,debounce-tolti,debounce-repsyscon-phy-powersyscon-pllreset#phy-cellssyscon-pcsphy-supplyutmi-modeinterrupt-namesmaximum-speeddr_modesnps,dis_u3_susphy_quirksnps,dis_u2_susphy_quirkgpmc,num-csgpmc,num-waitpinsti,provided-clockspinctrl-1op-modetdm-slotsserial-dirti,max-irqsti,max-crossbar-sourcesti,reg-sizeti,irqs-reservedti,irqs-skipti,irqs-safe-mapcpdma_channelsale_entriesbd_ram_sizeno_bd_ramrx_descsmac_controlslavesactive_slavecpts_clock_multcpts_clock_shiftti,no-idledual_emacbus_freqmac-addressphy_idphy-modedual_emac_res_vlansyscon-raminitsyscon-pll-ctrlsyscon-polpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-deviceoperating-pointsclock-latencycooling-min-levelcooling-max-level#cooling-cellscpu0-supplyvoltage-tolerancegpioslinux,default-triggerdefault-statesimple-audio-card,namesimple-audio-card,formatsimple-audio-card,bitclock-mastersimple-audio-card,frame-mastersimple-audio-card,widgetssimple-audio-card,routingsound-daisystem-clock-frequency