;80( ~/Ncompulab,sbc-am57xcompulab,cl-som-am57xti,am5728ti,dra742ti,dra74ti,dra7&&7CompuLab CL-SOM-AM57x on SB-SOM-AM57xchosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/i2c@4807a000Q/ocp/i2c@4807c000V/ocp/serial@4806a000^/ocp/serial@4806c000f/ocp/serial@48020000n/ocp/serial@4806e000v/ocp/serial@48066000~/ocp/serial@48068000/ocp/serial@48420000/ocp/serial@48422000/ocp/serial@48424000/ocp/serial@4ae2b000&/ocp/ethernet@48484000/slave@48480200&/ocp/ethernet@48484000/slave@48480300/ocp/can@481cc000/ocp/can@481d0000/ocp/qspi@4b300000 /display#/ocp/dss@58000000/encoder@58060000memorymemory timerarm,armv7-timer0   &interrupt-controller@48211000arm,cortex-a15-gic@H!H! H!@ H!`   & &interrupt-controller@48281000&ti,omap5-wugen-mputi,omap4-wugen-mpuH(& &socti,omap-inframpu ti,omap5-mpu.mpuocpti,dra7-l3-nocsimple-bus8.l3_main_1l3_main_2 DE ? l4@4a000000ti,dra7-l4-cfgsimple-bus 8J"scm@2000ti,dra7-scm-coresimple-bus  8 scm_conf@0sysconsimple-bus 8 &pbias_regulatorti,pbias-dra7ti,pbias-omapSpbias_mmc_omap5Zpbias_mmc_omap5iw@- &clocksdss_deshdcp_clkti,gate-clockXehrpwm0_tbclkti,gate-clockXehrpwm1_tbclkti,gate-clockXehrpwm2_tbclkti,gate-clockXsys_32k_ck ti,mux-clock G&Gpinmux@1400ti,dra7-padconfpinctrl-singleh ? &leds_pins_default| &i2c1_pins_default &i2c3_pins_default   &i2c4_pins_default   &tps659038_pins_default &mmc2_pins_defaultP &pinmux_qspi1_pins0t &cpsw_pins_defaultPTX\`dhlptx| &cpsw_pins_sleepPTX\`dhlptx| &davinci_mdio_pins_default &davinci_mdio_pins_sleep &pinmux_ads7846_pinsd &mcasp3_pins_default $(,0 &mcasp3_pins_sleep $(,0 &uart3_pins_defaultH L  &mmc1_pins_default@TX\`dhl| &pinmux_usb1_pins  &i2c5_pins_default   &lcd_pins_defaultd &pinmux_hdmi_pins  &pinmux_hdmi_conn_pins &scm_conf@1c04syscon scm_conf@1c24syscon$$ &cm_core_aon@5000ti,dra7-cm-core-aonP clocksatl_clkin0_ckti,dra7-atl-clock  :&:atl_clkin1_ckti,dra7-atl-clock  9&9atl_clkin2_ckti,dra7-atl-clock  8&8atl_clkin3_ckti,dra7-atl-clock  7&7hdmi_clkin_ck fixed-clock  (&(mlb_clkin_ck fixed-clock  &mlbp_clkin_ck fixed-clock  &pciesref_acs_clk_ck fixed-clock  Q&Qref_clkin0_ck fixed-clock  <&<ref_clkin1_ck fixed-clock  =&=ref_clkin2_ck fixed-clock  >&>ref_clkin3_ck fixed-clock  ?&?rmii_clk_ck fixed-clock sdvenc_clkin_ck fixed-clock secure_32k_clk_src_ck fixed-clock  &sys_clk32_crystal_ck fixed-clock  &sys_clk32_pseudo_ckfixed-factor-clock $b &virt_12000000_ck fixed-clock  u&uvirt_13000000_ck fixed-clock ]@virt_16800000_ck fixed-clock Y w&wvirt_19200000_ck fixed-clock $ x&xvirt_20000000_ck fixed-clock 1- v&vvirt_26000000_ck fixed-clock  y&yvirt_27000000_ck fixed-clock  z&zvirt_38400000_ck fixed-clock I {&{sys_clkin2 fixed-clock X ;&;usb_otg_clkin_ck fixed-clock  &video1_clkin_ck fixed-clock  1&1video1_m2_clkin_ck fixed-clock  '&'video2_clkin_ck fixed-clock  2&2video2_m2_clkin_ck fixed-clock  &&&dpll_abe_ckti,omap4-dpll-m4xen-clock  & dpll_abe_x2_ckti,omap4-dpll-x2-clock  &dpll_abe_m2x2_ckti,divider-clock.9Kb &abe_clkti,divider-clock.y }&}dpll_abe_m2_ckti,divider-clock .9Kb f&fdpll_abe_m3x2_ckti,divider-clock.9Kb &dpll_core_byp_mux ti,mux-clock , &dpll_core_ckti,omap4-dpll-core-clock  $,( &dpll_core_x2_ckti,omap4-dpll-x2-clock &dpll_core_h12x2_ckti,divider-clock.?9<Kb &mpu_dpll_hs_clk_divfixed-factor-clock$ &dpll_mpu_ckti,omap5-mpu-dpll-clock `dlh &dpll_mpu_m2_ckti,divider-clock.9pKb &mpu_dclk_divfixed-factor-clock$ &dsp_dpll_hs_clk_divfixed-factor-clock$ &dpll_dsp_byp_mux ti,mux-clock @ &dpll_dsp_ckti,omap4-dpll-clock 48@< &dpll_dsp_m2_ckti,divider-clock.9DKb &iva_dpll_hs_clk_divfixed-factor-clock$ &dpll_iva_byp_mux ti,mux-clock  &dpll_iva_ckti,omap4-dpll-clock  &dpll_iva_m2_ckti,divider-clock.9Kb &iva_dclkfixed-factor-clock$ &dpll_gpu_byp_mux ti,mux-clock  &dpll_gpu_ckti,omap4-dpll-clock  & dpll_gpu_m2_ckti,divider-clock .9Kb k&kdpll_core_m2_ckti,divider-clock.90Kb !&!core_dpll_out_dclk_divfixed-factor-clock!$ &dpll_ddr_byp_mux ti,mux-clock  "&"dpll_ddr_ckti,omap4-dpll-clock " #&#dpll_ddr_m2_ckti,divider-clock#.9 Kb &dpll_gmac_byp_mux ti,mux-clock  $&$dpll_gmac_ckti,omap4-dpll-clock $ %&%dpll_gmac_m2_ckti,divider-clock%.9Kb h&hvideo2_dclk_divfixed-factor-clock&$ &video1_dclk_divfixed-factor-clock'$ &hdmi_dclk_divfixed-factor-clock($ &per_dpll_hs_clk_divfixed-factor-clock$ U&Uusb_dpll_hs_clk_divfixed-factor-clock$ Y&Yeve_dpll_hs_clk_divfixed-factor-clock$ )&)dpll_eve_byp_mux ti,mux-clock ) *&*dpll_eve_ckti,omap4-dpll-clock * +&+dpll_eve_m2_ckti,divider-clock+.9Kb ,&,eve_dclk_divfixed-factor-clock,$ &dpll_core_h13x2_ckti,divider-clock.?9@Kbdpll_core_h14x2_ckti,divider-clock.?9DKb i&idpll_core_h22x2_ckti,divider-clock.?9TKb 3&3dpll_core_h23x2_ckti,divider-clock.?9XKb t&tdpll_core_h24x2_ckti,divider-clock.?9\Kbdpll_ddr_x2_ckti,omap4-dpll-x2-clock# -&-dpll_ddr_h11x2_ckti,divider-clock-.?9(Kbdpll_dsp_x2_ckti,omap4-dpll-x2-clock .&.dpll_dsp_m3x2_ckti,divider-clock..9HKb &dpll_gmac_x2_ckti,omap4-dpll-x2-clock% /&/dpll_gmac_h11x2_ckti,divider-clock/.?9Kb 0&0dpll_gmac_h12x2_ckti,divider-clock/.?9Kbdpll_gmac_h13x2_ckti,divider-clock/.?9Kbdpll_gmac_m3x2_ckti,divider-clock/.9Kbgmii_m_clk_divfixed-factor-clock0$hdmi_clk2_divfixed-factor-clock($ E&Ehdmi_div_clkfixed-factor-clock($ K&Kl3_iclk_divti,divider-clock.y &l4_root_clk_divfixed-factor-clock$ &video1_clk2_divfixed-factor-clock1$ C&Cvideo1_div_clkfixed-factor-clock1$ I&Ivideo2_clk2_divfixed-factor-clock2$ D&Dvideo2_div_clkfixed-factor-clock2$ J&Jipu1_gfclk_mux ti,mux-clock3 mcasp1_ahclkr_mux ti,mux-clock8456789:;<=>?@APmcasp1_ahclkx_mux ti,mux-clock8456789:;<=>?@APmcasp1_aux_gfclk_mux ti,mux-clockBCDEPtimer5_gfclk_mux ti,mux-clock0FG;<=>?HIJKLXtimer6_gfclk_mux ti,mux-clock0FG;<=>?HIJKL`timer7_gfclk_mux ti,mux-clock0FG;<=>?HIJKLhtimer8_gfclk_mux ti,mux-clock0FG;<=>?HIJKLpuart6_gfclk_mux ti,mux-clockMNdummy_ck fixed-clock clockdomainscm_core@8000ti,dra7-cm-core0clocksdpll_pcie_ref_ckti,omap4-dpll-clock   O&Odpll_pcie_ref_m2ldo_ckti,divider-clockO.9Kb P&Papll_pcie_in_clk_mux@4ae06118 ti,mux-clockPQ R&Rapll_pcie_ckti,dra7-apll-clockRO  S&Soptfclk_pciephy1_32khz@4a0093b0ti,gate-clockG &optfclk_pciephy2_32khz@4a0093b8ti,gate-clockG &optfclk_pciephy_div@4a00821cti,divider-clockS. T&Toptfclk_pciephy1_clk@4a0093b0ti,gate-clockS  &optfclk_pciephy2_clk@4a0093b8ti,gate-clockS  &optfclk_pciephy1_div_clk@4a0093b0ti,gate-clockT  &optfclk_pciephy2_div_clk@4a0093b8ti,gate-clockT  &apll_pcie_clkvcoldofixed-factor-clockS$apll_pcie_clkvcoldo_divfixed-factor-clockS$apll_pcie_m2_ckfixed-factor-clockS$ &dpll_per_byp_mux ti,mux-clock UL V&Vdpll_per_ckti,omap4-dpll-clock V@DLH W&Wdpll_per_m2_ckti,divider-clockW.9PKb X&Xfunc_96m_aon_dclk_divfixed-factor-clockX$ &dpll_usb_byp_mux ti,mux-clock Y Z&Zdpll_usb_ckti,omap4-dpll-j-type-clock Z [&[dpll_usb_m2_ckti,divider-clock[.9Kb ^&^dpll_pcie_ref_m2_ckti,divider-clockO.9Kb &dpll_per_x2_ckti,omap4-dpll-x2-clockW \&\dpll_per_h11x2_ckti,divider-clock\.?9XKb ]&]dpll_per_h12x2_ckti,divider-clock\.?9\Kb a&adpll_per_h13x2_ckti,divider-clock\.?9`Kb r&rdpll_per_h14x2_ckti,divider-clock\.?9dKb j&jdpll_per_m2x2_ckti,divider-clock\.9PKb N&Ndpll_usb_clkdcoldofixed-factor-clock[$ `&`func_128m_clkfixed-factor-clock]$ m&mfunc_12m_fclkfixed-factor-clockN$func_24m_clkfixed-factor-clockX$ 6&6func_48m_fclkfixed-factor-clockN$ M&Mfunc_96m_fclkfixed-factor-clockN$l3init_60m_fclkti,divider-clock^clkout2_clkti,gate-clock_l3init_960m_gfclkti,gate-clock` e&edss_32khz_clkti,gate-clockG  dss_48mhz_clkti,gate-clockM   &dss_dss_clkti,gate-clocka  &dss_hdmi_clkti,gate-clockb   &dss_video1_clkti,gate-clockc   &dss_video2_clkti,gate-clockd   &gpio2_dbclkti,gate-clockG`gpio3_dbclkti,gate-clockGhgpio4_dbclkti,gate-clockGpgpio5_dbclkti,gate-clockGxgpio6_dbclkti,gate-clockGgpio7_dbclkti,gate-clockGgpio8_dbclkti,gate-clockGmmc1_clk32kti,gate-clockG(mmc2_clk32kti,gate-clockG0mmc3_clk32kti,gate-clockG mmc4_clk32kti,gate-clockG(sata_ref_clkti,gate-clock  &usb_otg_ss1_refclk960mti,gate-clocke &usb_otg_ss2_refclk960mti,gate-clocke@ &usb_phy1_always_on_clk32kti,gate-clockG@ &usb_phy2_always_on_clk32kti,gate-clockG &usb_phy3_always_on_clk32kti,gate-clockG &atl_dpll_clk_mux ti,mux-clockG12(  g&gatl_gfclk_mux ti,mux-clock fg  & gmac_gmii_ref_clk_divti,divider-clockh &gmac_rft_clk_mux ti,mux-clock12f(gpu_core_gclk_mux ti,mux-clock ijk gpu_hyd_gclk_mux ti,mux-clock ijk l3instr_ts_gclk_divti,divider-clocklP  mcasp2_ahclkr_mux ti,mux-clock8456789:;<=>?@A`mcasp2_ahclkx_mux ti,mux-clock8456789:;<=>?@A`mcasp2_aux_gfclk_mux ti,mux-clockBCDE`mcasp3_ahclkx_mux ti,mux-clock8456789:;<=>?@Ah &mcasp3_aux_gfclk_mux ti,mux-clockBCDEh &mcasp4_ahclkx_mux ti,mux-clock8456789:;<=>?@Amcasp4_aux_gfclk_mux ti,mux-clockBCDEmcasp5_ahclkx_mux ti,mux-clock8456789:;<=>?@Axmcasp5_aux_gfclk_mux ti,mux-clockBCDExmcasp6_ahclkx_mux ti,mux-clock8456789:;<=>?@Amcasp6_aux_gfclk_mux ti,mux-clockBCDEmcasp7_ahclkx_mux ti,mux-clock8456789:;<=>?@Amcasp7_aux_gfclk_mux ti,mux-clockBCDEmcasp8_ahclk_mux ti,mux-clock8456789:;<=>?@Amcasp8_aux_gfclk_mux ti,mux-clockBCDEmmc1_fclk_mux ti,mux-clockmN( n&nmmc1_fclk_divti,divider-clockn.(ymmc2_fclk_mux ti,mux-clockmN0 o&ommc2_fclk_divti,divider-clocko.0ymmc3_gfclk_mux ti,mux-clockMN  p&pmmc3_gfclk_divti,divider-clockp. ymmc4_gfclk_mux ti,mux-clockMN( q&qmmc4_gfclk_divti,divider-clockq.(yqspi_gfclk_mux ti,mux-clockmr8 s&sqspi_gfclk_divti,divider-clocks.8y &timer10_gfclk_mux ti,mux-clock,FG;<=>?HIJK(timer11_gfclk_mux ti,mux-clock,FG;<=>?HIJK0timer13_gfclk_mux ti,mux-clock,FG;<=>?HIJKtimer14_gfclk_mux ti,mux-clock,FG;<=>?HIJKtimer15_gfclk_mux ti,mux-clock,FG;<=>?HIJKtimer16_gfclk_mux ti,mux-clock,FG;<=>?HIJK0timer2_gfclk_mux ti,mux-clock,FG;<=>?HIJK8timer3_gfclk_mux ti,mux-clock,FG;<=>?HIJK@timer4_gfclk_mux ti,mux-clock,FG;<=>?HIJKHtimer9_gfclk_mux ti,mux-clock,FG;<=>?HIJKPuart1_gfclk_mux ti,mux-clockMN@uart2_gfclk_mux ti,mux-clockMNHuart3_gfclk_mux ti,mux-clockMNPuart4_gfclk_mux ti,mux-clockMNXuart5_gfclk_mux ti,mux-clockMNpuart7_gfclk_mux ti,mux-clockMNuart8_gfclk_mux ti,mux-clockMNuart9_gfclk_mux ti,mux-clockMNvip1_gclk_mux ti,mux-clockt vip2_gclk_mux ti,mux-clockt(vip3_gclk_mux ti,mux-clockt0clockdomainscoreaon_clkdmti,clockdomain[l4@4ae00000ti,dra7-l4-wkupsimple-bus 8Jcounter@4000ti,omap-counter32k@@ .counter_32kprm@6000 ti,dra7-prm`0 clockssys_clkin1 ti,mux-clockuvwxyz{K & abe_dpll_sys_clk_mux ti,mux-clock ; |&|abe_dpll_bypass_clk_mux ti,mux-clock|G & abe_dpll_clk_mux ti,mux-clock|G  & abe_24m_fclkti,divider-clock 4&4aess_fclkti,divider-clock}x. ~&~abe_giclk_divti,divider-clock~t. H&Habe_lp_clk_divti,divider-clock  &abe_sys_clk_divti,divider-clock  . 5&5adc_gfclk_mux ti,mux-clock  ;Gsys_clk1_dclk_divti,divider-clock .@y &sys_clk2_dclk_divti,divider-clock;.@y &per_abe_x1_dclk_divti,divider-clockf.@y &dsp_gclk_divti,divider-clock.@y &gpu_dclkti,divider-clockk.@y &emif_phy_dclk_divti,divider-clock.@y &gmac_250m_dclk_divti,divider-clockh.@y &l3init_480m_dclk_divti,divider-clock^.@y &usb_otg_dclk_divti,divider-clock.@y &sata_dclk_divti,divider-clock .@y &pcie2_dclk_divti,divider-clock.@y &pcie_dclk_divti,divider-clock.@y &emu_dclk_divti,divider-clock .@y &secure_32k_dclk_divti,divider-clock.@y &clkoutmux0_clk_mux ti,mux-clockXX L&Lclkoutmux1_clk_mux ti,mux-clockX\clkoutmux2_clk_mux ti,mux-clockX` _&_custefuse_sys_gfclk_divfixed-factor-clock $eve_clk ti,mux-clock,hdmi_dpll_clk_mux ti,mux-clock ;d b&bmlb_clkti,divider-clock.@4y @&@mlbp_clkti,divider-clock.@0y A&Aper_abe_x1_gfclk2_divti,divider-clockf.@8y B&Btimer_sys_clk_divti,divider-clock D. F&Fvideo1_dpll_clk_mux ti,mux-clock ;h c&cvideo2_dpll_clk_mux ti,mux-clock ;l d&dwkupaon_iclk_mux ti,mux-clock  l&lgpio1_dbclkti,gate-clockG8dcan1_sys_clk_mux ti,mux-clock ; &timer1_gfclk_mux ti,mux-clock,FG;<=>?HIJK@uart10_gfclk_mux ti,mux-clockMNclockdomainsaxi@0 simple-bus8QQ0 pcie@51000000 ti,dra7-pcieQ Q L rc_dbicsti_confconfigpci080 00.pcie1 pcie-phy0`interrupt-controller &axi@1 simple-bus8QQ00 disabledpcie@51000000 ti,dra7-pcieQ Q L rc_dbicsti_confconfigcdpci080000.pcie2 pcie-phy0`interrupt-controller &bandgap@4a0021e00J! J#, J#,J#txrxokaydefault  mmc@480b4000ti,omap4-hsmmcH @ Q.mmc2/0txrxokaydefaultmmc@480ad000ti,omap4-hsmmcH  Y.mmc3MNtxrx disabledmmc@480d1000ti,omap4-hsmmcH  [.mmc49:txrx disabledmmu@40d01000ti,dra7-dsp-iommu@  .mmu0_dsp1 disabledmmu@40d02000ti,dra7-dsp-iommu@   .mmu1_dsp1 disabledmmu@58882000ti,dra7-iommuX   .mmu_ipu12 disabledmmu@55082000ti,dra7-iommuU   .mmu_ipu22 disabledregulator-abb-mpu ti,abb-v3Zabb_mpu H2Y(J}J}J`J; JXDsetup-addresscontrol-addressint-addressefuse-addressldo-addressiH,@vregulator-abb-ivahd ti,abb-v3 Zabb_ivahd H2Y(J~4J~$J`J% J$pDsetup-addresscontrol-addressint-addressefuse-addressldo-addressi@H0regulator-abb-dspeve ti,abb-v3 Zabb_dspeve H2Y(J~0J~ J`J% J$lDsetup-addresscontrol-addressint-addressefuse-addressldo-addressi H0regulator-abb-gpu ti,abb-v3Zabb_gpu H2Y(J}J}J`J; JTDsetup-addresscontrol-addressint-addressefuse-addressldo-addressiHvspi@48098000ti,omap4-mcspiH  <.mcspi1@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3 disabledspi@4809a000ti,omap4-mcspiH  =.mcspi2 +,-.tx0rx0tx1rx1 disabledspi@480b8000ti,omap4-mcspiH  V.mcspi3tx0rx0 disabledspi@480ba000ti,omap4-mcspiH  +.mcspi4FGtx0rx0 disabledqspi@4b300000ti,dra7xxx-qspiK0\qspi_baseqspi_mmapX.qspifck Wokaydefaultlspi_flash@0spansion,m25p80jedec,spi-norlpartition@0uboot partition@c0000uboot environment partition@100000 reservedads7846@0default ti,ads7846`&   )2;K[k {Kocp2scp@4a090000ti,omap-ocp2scp8J  .ocp2scp3phy@4A096000ti,phy-pipe3-sataJ `J ddJ h@phy_rxphy_txpll_ctrlt sysclkrefclk &pciephy@4a094000ti,phy-pipe3-pcieJ @J Ddphy_rxphy_txOPT ;dpll_refdpll_ref_m2wkupclkrefclkdiv-clkphy-divsysclk &pciephy@4a095000ti,phy-pipe3-pcieJ PJ Tdphy_rxphy_tx OPT ;dpll_refdpll_ref_m2wkupclkrefclkdiv-clkphy-divsysclk disabled &sata@4a141100snps,dwc-ahciJJ 1 sata-phy.sataokayrtc@48838000ti,am3352-rtcH.rtcssGocp2scp@4a080000ti,omap-ocp2scp8J  .ocp2scp1phy@4a084000 ti,omap-usb2J@wkupclkrefclk &phy@4a085000 ti,dra7x-usb2-phy2ti,omap-usb2JPtwkupclkrefclk &phy@4a084400 ti,omap-usb3JDJHdJL@phy_rxphy_txpll_ctrlp  wkupclksysclkrefclk &omap_dwc3_1@48880000ti,dwc3 .usb_otg_ss1H H8usb@48890000 snps,dwc3Hp$GGHperipheralhostotgusb2-phyusb3-phy super-speedhostdefaultomap_dwc3_2@488c0000ti,dwc3 .usb_otg_ss2H W8usb@488d0000 snps,dwc3Hp$IIWperipheralhostotg usb2-phy high-speedhostomap_dwc3_3@48900000ti,dwc3 .usb_otg_ss3H X8 disabledusb@48910000 snps,dwc3Hp$XXXperipheralhostotg high-speedotgelm@48078000ti,am3352-elmH .elm disabledgpmc@50000000ti,am3352-gpmc.gpmcP| /; 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