RTHL4( Ksamtec VIN|ING FPGA1!samtec,viningaltr,socfpga-cyclone5altr,socfpgaaliases,/soc/ethernet@ff7020006/soc/ethernet@ff700000@/soc/serial0@ffc02000H/soc/serial1@ffc03000P/soc/timer0@ffc08000W/soc/timer1@ffc09000^/soc/timer2@ffd00000e/soc/timer3@ffd01000cpuslaltr,socfpga-smpcpu@0!arm,cortex-a9zcpucpu@1!arm,cortex-a9zcpupmu@ff111000!arm,cortex-a9-pmu0intc@fffed000!arm,cortex-a9-gicsoc !simple-buszsocamba !simple-buspdma@ffe01000!arm,pl330arm,primecell`hijklmno , 3apb_pclk22base_fpga_region !fpga-region?can@ffc00000 !bosch,d_can0, Hdisabledcan@ffc01000 !bosch,d_can0, Hdisabledclkmgr@ffd04000 !altr,clk-mgr@clocksosc1O !fixed-clock\}x@  osc2O !fixed-clock  f2s_periph_ref_clkO !fixed-clock  f2s_sdram_ref_clkO !fixed-clockmain_pll@40O!altr,socfpga-pll-clock, @  mpuclk@48O!altr,socfpga-perip-clk,  l Hmainclk@4cO!altr,socfpga-perip-clk,  l Ldbg_base_clk@50O!altr,socfpga-perip-clk,  l Pmain_qspi_clk@54O!altr,socfpga-perip-clk, Tmain_nand_sdmmc_clk@58O!altr,socfpga-perip-clk, Xcfg_h2f_usr0_clk@5cO!altr,socfpga-perip-clk, \periph_pll@80O!altr,socfpga-pll-clock ,   emac0_clk@88O!altr,socfpga-perip-clk, emac1_clk@8cO!altr,socfpga-perip-clk, per_qsi_clk@90O!altr,socfpga-perip-clk, per_nand_mmc_clk@94O!altr,socfpga-perip-clk, per_base_clk@98O!altr,socfpga-perip-clk, h2f_usr1_clk@9cO!altr,socfpga-perip-clk, sdram_pll@c0O!altr,socfpga-pll-clock , ddr_dqs_clk@c8O!altr,socfpga-perip-clk,ddr_2x_dqs_clk@ccO!altr,socfpga-perip-clk,  ddr_dq_clk@d0O!altr,socfpga-perip-clk,!!h2f_usr2_clk@d4O!altr,socfpga-perip-clk,""mpu_periph_clkO!altr,socfpga-perip-clk,t11mpu_l2_ram_clkO!altr,socfpga-perip-clk,tl4_main_clkO!altr,socfpga-gate-clk,`l3_main_clkO!altr,socfpga-perip-clk,tl3_mp_clkO!altr,socfpga-gate-clk, ld`l3_sp_clkO!altr,socfpga-gate-clk, ldl4_mp_clkO!altr,socfpga-gate-clk, ld`))l4_sp_clkO!altr,socfpga-gate-clk, ld`**dbg_at_clkO!altr,socfpga-gate-clk, lh`dbg_clkO!altr,socfpga-gate-clk, lh`dbg_trace_clkO!altr,socfpga-gate-clk, ll`dbg_timer_clkO!altr,socfpga-gate-clk,`cfg_clkO!altr,socfpga-gate-clk,`h2f_user0_clkO!altr,socfpga-gate-clk,` emac_0_clkO!altr,socfpga-gate-clk,%%emac_1_clkO!altr,socfpga-gate-clk,&&usb_mp_clkO!altr,socfpga-gate-clk, l33spi_m_clkO!altr,socfpga-gate-clk, l00can0_clkO!altr,socfpga-gate-clk, lcan1_clkO!altr,socfpga-gate-clk, l gpio_db_clkO!altr,socfpga-gate-clk, lh2f_user1_clkO!altr,socfpga-gate-clk,sdmmc_clkO!altr,socfpga-gate-clk , sdmmc_clk_dividedO!altr,socfpga-gate-clk,t,,nand_x_clkO!altr,socfpga-gate-clk ,  nand_clkO!altr,socfpga-gate-clk ,  t--qspi_clkO!altr,socfpga-gate-clk ,  ..ddr_dqs_clk_gateO!altr,socfpga-gate-clk,ddr_2x_dqs_clk_gateO!altr,socfpga-gate-clk, ddr_dq_clk_gateO!altr,socfpga-gate-clk,!h2f_user2_clkO!altr,socfpga-gate-clk,"fpga_bridge@ff400000!altr,socfpga-lwhps2fpga-bridge@#a,fpga_bridge@ff500000!altr,socfpga-hps2fpga-bridgeP#`,fpgamgr@ff706000!altr,socfpga-fpga-mgrp` ethernet@ff7000000!altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmac $`p  smacirq,% 3stmmaceth#  stmmaceth Hdisabledethernet@ff7020000!altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmac $`p  xmacirq,& 3stmmaceth#! stmmacethHokay*rgmii3' >(N d'''mdio0!snps,dwmac-mdioethernet-phy@1y (''gpio@ff708000!snps,dw-apb-gpiop,)Hokaygpio-controller@0!snps,dw-apb-gpio-port ((gpio@ff709000!snps,dw-apb-gpiop,)Hokaygpio-controller@0!snps,dw-apb-gpio-port 66gpio@ff70a000!snps,dw-apb-gpiop,)Hokaygpio-controller@0!snps,dw-apb-gpio-port 55i2c@ffc04000!snps,designware-i2c@,* Hokaypca9557@1f !nxp,pca9557lm75@48!lm75Hat24@50 !at24,24c01 Pi2cswitch@70 !nxp,pca9548pi2c@0i2c@1i2c@2i2c@3i2c@4i2c@5i2c@6eeprom@51 !at,24c01 Qi2c@7eeprom@51 !at,24c01 Qi2c@ffc05000!snps,designware-i2cP,* Hokay\at24@50 !at24,24c02 Pi2c@ffc06000!snps,designware-i2c`,*  Hdisabledi2c@ffc07000!snps,designware-i2cp,*  Hdisabledeccmgr!altr,socfpga-ecc-managerl2-ecc@ffd08140!altr,socfpga-l2-eccЁ@$%ocram-ecc@ffd08144!altr,socfpga-ocram-eccЁD+l2-cache@fffef000!arm,pl310-cache &% 1 AR`ol3regs@0xff800000!altr,l3regssyscondwmmc0@ff704000!altr,socfpga-dw-mshcp@ ,),3biuciu Hdisabled nand@ff900000!denali,denali-nand-dt0nand_datadenali_reg :,- Hdisabledsram@ffff0000 !mmio-sram++spi@ff705000!cdns,qspi-norpP CSc,.Hokayn25q128@0!n25q128x22n25q00@1!n25q00x22rstmgr@ffd05000 !altr,rst-mgrP ##snoop-control-unit@fffec000!arm,cortex-a9-scusdr@ffc25000!altr,sdr-ctlsysconP//sdramedac!altr,sdram-edac / 'spi@fff00000!snps,dw-apb-ssi 0,0 Hdisabledspi@fff01000!snps,dw-apb-ssi 0,0 Hdisabledsysmgr@ffd08000!altr,sys-mgrsysconЀ@7Ѐ$$timer@fffec600!arm,cortex-a9-twd-timer  ,1timer0@ffc08000!snps,dw-apb-timer ,*3timertimer1@ffc09000!snps,dw-apb-timer ,*3timertimer2@ffd00000!snps,dw-apb-timer , 3timertimer3@ffd01000!snps,dw-apb-timer , 3timerserial0@ffc02000!snps,dw-apb-uart  GQ,*^22ctxrxserial1@ffc03000!snps,dw-apb-uart0 GQ,*^22ctxrxusbphym!usb-nop-xceivHokay44usb@ffb00000 !snps,dwc2 },33otg#"dwc2x4 }usb2-phyHokayhostusb@ffb40000 !snps,dwc2 ,33otg##dwc2x4 }usb2-phyHokay peripheralwatchdog@ffd02000 !snps,dw-wdt  , Hokaywatchdog@ffd03000 !snps,dw-wdt0 ,  Hdisabledchosenconsole=ttyS0,115200memory@0zmemory@gpio-keys !gpio-keyshps_temp0BTN_0 5hps_hkey0BTN_1 5hps_hkey1 hps_hkey1 5tregulator-usb-nrst!regulator-fixed usb_nrstLK@LK@ I6p  #address-cells#size-cellsmodelcompatibleethernet0ethernet1serial0serial1timer0timer1timer2timer3enable-methoddevice_typeregnext-level-cachelinux,phandleinterrupt-parentinterruptsinterrupt-affinity#interrupt-cellsinterrupt-controllerranges#dma-cells#dma-channels#dma-requestsclocksclock-namesfpga-mgrstatus#clock-cellsclock-frequencydiv-regfixed-dividerclk-gateclk-phaseresetsaltr,sysmgr-sysconinterrupt-namesmac-addressreset-namessnps,multicast-filter-binssnps,perfect-filter-entriestx-fifo-depthrx-fifo-depthphy-modephy-handlesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usrxd0-skew-psrxd1-skew-psrxd2-skew-psrxd3-skew-pstxen-skew-pstxc-skew-psrxdv-skew-psrxc-skew-psgpio-controller#gpio-cellssnps,nr-gpiospagesizeiramcache-unifiedcache-levelarm,tag-latencyarm,data-latencyprefetch-dataprefetch-instrarm,shared-overridearm,double-linefillarm,double-linefill-incrarm,double-linefill-wraparm,prefetch-droparm,prefetch-offsetnum-slotsbroken-cdbus-widthcap-mmc-highspeedcap-sd-highspeedreg-namesdma-maskcdns,fifo-depthcdns,fifo-widthcdns,trigger-addressspi-max-frequencym25p,fast-readcdns,page-sizecdns,block-sizecdns,read-delaycdns,tshsl-nscdns,tsd2d-nscdns,tchsh-nscdns,tslch-ns#reset-cellsaltr,modrst-offsetaltr,sdr-sysconnum-cscpu1-start-addrreg-shiftreg-io-widthdmasdma-names#phy-cellsphysphy-namesdr_modebootargslabellinux,coderegulator-nameregulator-min-microvoltregulator-max-microvoltstartup-delay-usenable-active-highregulator-always-on