Š žķE}8@ģ(‘@“Synology DS1164!marvell,a385-gpmarvell,armada385marvell,armada380aliases,/soc/internal-regs/gpio@181002/soc/internal-regs/gpio@18140 8/soc/internal-regs/serial@12000 @/soc/internal-regs/serial@12100pmu!arm,cortex-a9-pmuHsoc"!marvell,armada380-mbussimple-bus\gxąŠčP›šń’š ń ń ń bootrom!marvell,bootrom ¢ devbus-bootcs!marvell,mvebu-devbus ¢š›/’’’’¦ ­disableddevbus-cs0!marvell,mvebu-devbus ¢š›>’’’’¦ ­disableddevbus-cs1!marvell,mvebu-devbus ¢š›=’’’’¦ ­disableddevbus-cs2!marvell,mvebu-devbus ¢š›;’’’’¦ ­disableddevbus-cs3!marvell,mvebu-devbus ¢š ›7’’’’¦ ­disabledinternal-regs !simple-bus›šcache-controller@8000!arm,pl310-cache¢€“ĀĪēscu@c000!arm,cortex-a9-scu¢ĄXtimer@c200!arm,cortex-a9-global-timer¢Ā  " ¦timer@c600!arm,cortex-a9-twd-timer¢Ę  " ¦interrupt-controller@d000!arm,cortex-a9-gic->¢ŠĮSi2c@11000+!marvell,mv78230-a0-i2cmarvell,mv64xxx-i2c¢  "[覭okayfdefaultt~† eeprom@57 !atmel,24c64¢Wi2c@11100+!marvell,mv78230-a0-i2cmarvell,mv64xxx-i2c¢  "[č¦ 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ĆgpiopwmĶŌäš>-0":;<=¦Ssystem-controller@18200M!marvell,armada-380-system-controllermarvell,armada-370-xp-system-controller¢‚clock-gating-control@18220 !marvell,armada-380-gating-clock¢‚ ¦ūS phy@18300!marvell,armada-380-comphy¢ƒphy@0¢phy@1¢phy@2¢phy@3¢phy@4¢phy@5¢mvebu-sar@18600!marvell,armada-380-core-clock¢†ūSmbus-controller@20000!marvell,mbus-controller¢€ PSinterrupt-controller@20a00 !marvell,mpic¢ ŠpX-> "Stimer@203001!marvell,armada-380-timermarvell,armada-xp-timer¢0@0PH    ¦ "nbclkfixedwatchdog@20300!marvell,armada-380-wdt¢4‚` ¦ "nbclkfixed H@ cpurst@20800!marvell,armada-370-cpu-reset¢mpcore-soc-ctrl@20d20#!marvell,armada-380-mpcore-soc-ctrl¢ lcoherency-fabric@21010$!marvell,armada-380-coherency-fabric¢pmsu@22000!marvell,armada-380-pmsu¢ ethernet@70000!marvell,armada-370-neta¢@H¦ .&H­okayfdefault< @sgmiiI Xethernet@30000!marvell,armada-370-neta¢@H ¦  ­disabledethernet@34000!marvell,armada-370-neta¢@@H ¦  ­disabledusb@58000!marvell,orion-ehci¢€ "¦  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usb3-vbus1fdefaultt,LK@DLK@\ oSpwr-sata0!regulator-fixed pwr_en_sata0,·D·\t oSv5-sata0!regulator-fixed v5.0-sata0,LK@DLK@†Sv12-sata0!regulator-fixed v12.0-sata0,·D·† #address-cells#size-cellsmodelcompatiblegpio0gpio1serial0serial1interrupts-extendedcontrollerinterrupt-parentpcie-mem-aperturepcie-io-aperturerangesregclocksstatuscache-unifiedcache-levelarm,double-linefill-incrarm,double-linefill-wraparm,double-linefillprefetch-datainterrupts#interrupt-cellsinterrupt-controllerphandletimeout-mspinctrl-namespinctrl-0clock-frequencyreg-shiftreg-io-widthmarvell,pinsmarvell,functionreg-namesngpiosgpio-controller#gpio-cells#pwm-cells#clock-cells#phy-cellsmsi-controllerclock-namestx-csum-limitphyphy-modebuffer-managerbm,pool-longdmacap,memcpydmacap,xordmacap,memsetmarvell,crypto-sramsmarvell,crypto-sram-sizetarget-supplyinternal-memclock-output-namesmrvl,clk-delay-cyclesusb-phyno-memory-wccell-indexspi-max-frequencym25p,fast-readlabelread-onlydevice_typemsi-parentbus-rangeassigned-addressesinterrupt-map-maskinterrupt-mapmarvell,pcie-portmarvell,pcie-lanegpio-fan,speed-map#cooling-cellsdefault-stateenable-methodstdout-pathvcc-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltenable-active-highgpioregulator-boot-onvin-supply