Ð þíKÿ8F¨(WFpSolidRun Clearfog Pro A1d!solidrun,clearfog-pro-a1solidrun,clearfog-a1marvell,armada388marvell,armada385marvell,armada380aliases,/soc/internal-regs/gpio@181002/soc/internal-regs/gpio@18140 8/soc/internal-regs/serial@12000 @/soc/internal-regs/serial@12100"H/soc/internal-regs/ethernet@70000"R/soc/internal-regs/ethernet@30000"\/soc/internal-regs/ethernet@34000pmu!arm,cortex-a9-pmufsoc"!marvell,armada380-mbussimple-busz…–à¨èP¹ðñÿð ñ ñ ñ bootrom!marvell,bootrom À devbus-bootcs!marvell,mvebu-devbus Àð¹/ÿÿÿÿÄ Ëdisableddevbus-cs0!marvell,mvebu-devbus Àð¹>ÿÿÿÿÄ Ëdisableddevbus-cs1!marvell,mvebu-devbus Àð¹=ÿÿÿÿÄ Ëdisableddevbus-cs2!marvell,mvebu-devbus Àð¹;ÿÿÿÿÄ Ëdisableddevbus-cs3!marvell,mvebu-devbus Àð ¹7ÿÿÿÿÄ Ëdisabledinternal-regs !simple-bus¹ðcache-controller@8000!arm,pl310-cacheÀ€Òàì2scu@c000!arm,cortex-a9-scuÀÀXtimer@c200!arm,cortex-a9-global-timerÀ  @ Ätimer@c600!arm,cortex-a9-twd-timerÀÆ  @ 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mpp4mpp5"geqref-clk-pins-0mpp45"refref-clk-pins-1mpp46"refspi-pins-0mpp22mpp23mpp24mpp25"spi0spi-pins-1mpp56mpp57mpp58mpp59"spi1qnand-pinsNmpp22mpp34mpp23mpp33mpp38mpp28mpp40mpp42mpp35mpp36mpp25mpp30mpp32"devnand-rbmpp41"nanduart-pins-0 mpp0mpp1"ua0quart-pins-1 mpp19mpp20"ua1sdhci-pins<mpp48mpp49mpp50mpp52mpp53mpp54mpp55mpp57mpp58mpp59"sd0sata-pins-0mpp20"sata0sata-pins-1mpp19"sata1sata-pins-2mpp47"sata2sata-pins-3mpp44"sata3microsom-phy-clk-pinsmpp45"refqmicrosom-sdhci-pins$mpp21mpp28mpp37mpp38mpp39mpp40"sd0qi2c1-pins mpp26mpp27"i2c1qclearfog-sdhci-cd-pinsmpp20"gpioqmikro-pins mpp22mpp29"gpiomikro-spi-pinsmpp43"spi1q!mikro-uart-pins mpp24mpp25"ua1qclearfog-dsa0-clk-pinsmpp46"refqclearfog-dsa0-pins mpp23mpp41"gpioqspi1-cs-pinsmpp55"spi1q rear-button-pinsmpp34"gpioq$gpio@18100+!marvell,armada-370-gpiomarvell,orion-gpioÀ@À 3gpiopwm= ¬¼D\K0@5678Äqgpio@18140+!marvell,armada-370-gpiomarvell,orion-gpioÀ@@È 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#address-cells#size-cellsmodelcompatiblegpio0gpio1serial0serial1ethernet1ethernet2ethernet3interrupts-extendedcontrollerinterrupt-parentpcie-mem-aperturepcie-io-aperturerangesregclocksstatuscache-unifiedcache-levelarm,double-linefill-incrarm,double-linefill-wraparm,double-linefillprefetch-datainterrupts#interrupt-cellsinterrupt-controllerphandletimeout-msclock-frequencypinctrl-0pinctrl-namesgpio-controller#gpio-cellsgpio-hoggpiosinputline-nameoutput-lowoutput-highreg-shiftreg-io-widthmarvell,pinsmarvell,functionreg-namesngpios#pwm-cells#clock-cells#phy-cellsmsi-controllerclock-namestx-csum-limitphyphy-modebuffer-managerbm,pool-longbm,pool-shortphysspeedfull-duplexmanagedsfpdmacap,memcpydmacap,xordmacap,memsetmarvell,reg-initlabelethernetmarvell,crypto-sramsmarvell,crypto-sram-sizeinternal-memclock-output-namesmrvl,clk-delay-cyclesbus-widthcd-gpiosno-1-8-vvmmc-supplywp-invertedno-memory-wccell-indexspi-max-frequencydevice_typemsi-parentbus-rangeassigned-addressesinterrupt-map-maskinterrupt-mapmarvell,pcie-portmarvell,pcie-lanereset-gpiosenable-methodstdout-pathregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-oni2c-buslos-gpiomod-def0-gpiotx-disable-gpiotx-fault-gpiomaximum-power-milliwattlinux,can-disablelinux,code